Abstract: A system and method are disclosed wherein a processor of a plurality of processors coupled to shared memory, is configured to initiate execution of a section of code according to a first transactional mode of the processor. The processor is configured to execute a plurality of protected memory access operations to the shared memory within the section of code as a single atomic transaction with respect to the plurality of processors. The processor is further configured to initiate, within the section of code, execution of a subsection of the section of code according to a second transactional mode of the processor, wherein the first and second transactional modes are each associated with respective recovery actions that the processor is configured to perform in response to detecting an abort condition.

Abstract: A computer-implemented method and article of manufacture is disclosed for enabling computer programs utilizing hardware transactional memory to safely interact with code utilizing traditional locks. A thread executing on a processor of a plurality of processors in a shared-memory system may initiate transactional execution of a section of code, which includes a plurality of access operations to the shared-memory, including one or more to locations protected by a lock. Before executing any operations accessing the location associated with the lock, the thread reads the value of the lock as part of the transaction, and only proceeds if the lock is not held. If the lock is acquired by another thread during transactional execution, the processor detects this acquisition, aborts the transaction, and attempts to re-execute it.

Abstract: A system and method for executing a transaction in a transactional memory system is disclosed. The system includes a processor of a plurality of processors coupled to shared memory, wherein the processor is configured to execute a section of code, including a plurality of memory access operations to the shared memory, as an atomic transaction relative to the execution of the plurality of processors. According to embodiments, the processor is configured to determine whether the memory access operations include any of a set of disallowed instructions, wherein the set includes one or more instructions that operate differently in a virtualized computing environment than in a native computing environment. If any of the memory access operations are ones of the disallowed instructions, then the processor aborts the transaction.

Abstract: A subsea wellhead assembly that includes a wellhead housing, a production tree, a tubing hanger adapted to land in the wellhead assembly inside the wellhead housing, and a bore formed through the production tree having an inner diameter greater than the tubing hanger outer diameter. A hanger adapter may be included having an annular body disposed on the tubing hanger upper surface and a flange member projecting radially outward from the annular body.

Abstract: A computer system includes a processor which may initialize a secure execution mode by executing a security initialization instruction. Further, the processor may operate in the secure execution mode by executing a secure operating system code segment. The computer system also includes an input/output (I/O) interface coupled to the processor via an I/O link. The I/O interface may receive transactions performed as a result of the execution of the security initialization instruction. The transactions include at least a portion of the secure operating system code segment. The I/O interface may also determine whether the processor is a source of the transactions. The computer system further includes a security services processor coupled to the I/O interface via a peripheral bus. The I/O interface may convey the transactions to the security services processor dependent upon determining that the processor is the source of the transactions.

Abstract: The initialization of a computer system including a secure execution mode-capable processor includes storing a secure operating system code segment loader to a plurality of locations corresponding to a particular range of addresses within a system memory. The method also includes executing a security initialization instruction. Executing the security initialization instruction may cause several operations to be performed including transmitting a start transaction including a base address of the particular range of addresses. In addition, executing the security instruction may also cause another operation to be performed including retrieving the secure operating system code segment loader from the system memory and transmitting the secure operating system code segment loader for validation as a plurality of data transactions.

Abstract: A wellhead assembly having a data sensor circuit for transmitting sensed data from within a wellbore to the well surface. The circuit includes a signal conduit axially inserted within the wall of a stab unit with connectors at the top and bottom portions of the stab unit. Corresponding connection leads are included within the wellhead assembly to connect with the stab unit connectors. The connectors may comprise a gallery ring wet connect.

Abstract: An apparatus for performing operations on an offshore well includes a subsea wellhead assembly. A riser extends from the subsea wellhead assembly to a surface vessel. A tool connects to a running string and is lowered through the riser into the wellhead assembly for performing operations at the wellhead assembly. A subsea controller is located adjacent the subsea wellhead assembly. The subsea controller controls the operation of the tool. A surface controller is positioned on the surface vessel, and is in communication with the subsea controller via a control line extending downward from the surface controller to the subsea controller. The control line extends downward from the surface controller along an exterior of the riser.

Abstract: A method for controlling operation of a secure execution mode-capable processor includes receiving access requests to a plurality of addressable locations within a system memory. The method may further include preventing the access requests from completing in response to determining that the secure execution mode-capable processor is operating in a secure execution mode.

Abstract: A method and system for handling a security exception. The method includes creating a security exception stack frame in secure memory at a base address. The method also includes writing a faulting code sequence address and one or more register values into the security exception stack frame, and executing a plurality of security exception instructions.

Abstract: A subsea well assembly has a tubing hanger that lands and seals in a wellhead housing. A tree block is lowered through the drilling riser into engagement with the tubing hanger. The tree block has a lower portion that inserts and latches into the bore of the wellhead housing. The drilling riser is disconnected, and a module is lowered onto the tree block, the module having a choke and controls for controlling the well. The master valve for production is the downhole safety valve in the tubing. The wing production valve is a ball valve located in the flow passage of the tree block.

Abstract: A method of controlling access to a control register of a microprocessor. The method of controlling access to a control register of a processor having a normal execution mode and a secure execution mode may include storing state and mode information in the control register, allowing a software invoked write access to modify the state and mode information within the control register during the normal execution mode and selectively inhibiting the software invoked write access during the secure execution mode.

Abstract: A method performing an operation in a subsea wellhead assembly through a riser extending between the wellhead assembly and a surface platform includes the step of connecting a surface blowout preventer to an upper portion of the riser. Then a tool is connected to a string of conduit. A control line is then connected to the tool, extended alongside the conduit. The tool and control line are lowered through the blowout preventer and riser. The method also includes the step of mounting a slick joint to an upper end of the conduit when the tool is near the wellhead assembly. The control line is then linked through the slick joint and extends to the surface platform. The method also includes the step of communicating with the tool via the control line and performing an operation in the wellhead assembly with the tool.

Abstract: A method is provided for controlling interrupts in a secure execution mode-capable processor. The method includes detecting an interrupt and performing a predetermined routine in response to detecting the interrupt. The method further includes performing a second routine prior to performing the predetermined routine in response to detecting the interrupt depending upon whether the processor is operating in a secure execution mode.

Abstract: A system is configured to selectively block peripheral accesses to system memory. The system includes a secure execution mode (SEM)-capable processor configured to operate in a trusted execution mode. The system also includes a system memory including a plurality of addressable locations. The system further includes a memory controller that may determine a source of an access request to one or more of the plurality of locations of the system memory. The memory controller may further allow the access request to proceed in response to determining that the source of the access request is the SEM-capable processor.

Abstract: Controlling access to a control register of a microprocessor. A method of controlling access to a control register such as CR3, for example, of a processor having a normal execution mode and a secure execution mode may include storing address translation table information in the control register, allowing a software invoked write access to modify the address translation table information during the normal execution mode and selectively inhibiting the software invoked write during the secure execution mode.

Abstract: A method of controlling a secure execution mode-capable processor includes allowing a plurality of interrupts to interrupt the secure execution mode-capable processor when the secure execution mode-capable processor is operating in a non-secure execution mode. The method also includes disabling the plurality of interrupts from interrupting the secure execution mode-capable processor when the secure execution mode-capable processor is operating in a secure execution mode.

Abstract: A processor executes a system call instruction. The processor includes at least two registers in which target addresses may be stored, and selects the target address from one of the registers responsive to the operating mode. Different target addresses may be programmed into the registers, and thus the operating mode of the code sequence may be indicated by which target address is selected.

Abstract: A method of controlling access to an address translation data structure of a computer system. The computer system includes a processor having a normal execution mode and a secure execution mode. The method includes executing code and generating a linear address. During translation of the linear address into a physical address, the method also includes generating a read-only page fault exception during the normal execution mode in response to detecting a software invoked write access to an address translation data structure having a read/write attribute set to be read-only. The method further includes selectively generating either the read-only page fault exception or a security exception during the secure execution mode in response to detecting the software invoked write access.

Abstract: A system and method for generating images of three-dimensional objects. The system includes one or more tracing processors, and one or more shading processors. Each of the tracing processors may be configured to (a) perform a first set of computations on a corresponding group of primary rays emanating from a viewpoint resulting in a ray tree and a set of one or more light trees for each primary ray of the corresponding group, (b) transfer the ray trees and associated light trees to one of the shading processors, and (c) repeat (a) and (b). Each of the shading processors may be configured to (d) receive ray trees and associated light trees from one of the tracing processors, (e) perform a second set of computations on the received ray trees and associated light trees to determine pixel color values, and (f) repeat (d) and (e) a plurality of times.