Abstract: Various implementations include circuits, devices and/or methods that provide open loop current limiting power amplifiers and the like. In some implementations, an open loop current clamp includes a trim module to provide a control value and a limiting source having respective input and output terminals. The input terminal is coupled to the trim module to receive the control value. The output terminal coupled to a control terminal of the first transistor to provide a limiting electrical level produced in response to the control value by the limiting source. The limiting electrical level substantially setting a first mode of operation for the first transistor such that the current draw of the first transistor is substantially determined by the first mode of operation and the limiting electrical level such that a voltage at an output terminal of the first transistor exerts reduced influence on the current draw.

Abstract: A radio frequency (RF) power amplification system in which a combination of a linear voltage regulator having a PFET pass device and a DC-DC converter having an NFET pass device is used to supply power to an RF power amplifier. The RF power amplifier receives power from either the linear voltage regular and its associated PFET pass device or the DC-DC converter and its NFET pass device, depending upon the condition of a mode signal.

Abstract: A system for pre-charging a current minor includes a controller configured to provide a first current and an additional current to a current minor to rapidly charge a capacitance associated with the current minor based on a reference voltage or control signals. A power amplifier module includes at least one current minor and a controller. A capacitor is coupled to the current minor. The controller provides a bias current in an amount proportional to an input to a voltage-to-current converter. The controller receives a control signal that directs the controller to apply one of a pre-charge voltage and a nominal voltage to the voltage-to-current converter.

Abstract: A system for power amplifier control saturation detection and correction includes a comparator configured to receive a power control signal and a detected power signal and generate a regulated voltage, a power amplifier configured to receive the regulated voltage and develop an output power, a power detector configured to sense the output power and develop the detected power signal, a saturation detector configured to receive the regulated voltage and a system voltage and determine whether the power amplifier is operating in a saturation mode during a transmit burst, and a current generator configured to reduce the power control signal when the power control signal exceeds a predetermined value and after expiration of a predetermined period of time, preventing the power control signal from exceeding the detected power signal.

Abstract: A system for power amplifier over-voltage protection includes a power amplifier configured to receive a system voltage, a bias circuit configured to provide a bias signal to the power amplifier, and a power amplifier over-voltage circuit configured to interrupt the bias signal when the system voltage exceeds a predetermined value, while the system voltage remains coupled to the power amplifier.

Abstract: A power amplifier gain control system that monitors power supply voltage and changes the gain of the amplifier in response to changes in supply voltage. In systems subject to changes in supply voltage, such as in a battery powered system, the supply voltage can change over time. Reductions in the supply voltage may force the amplifier out of linear operation. A detector circuit compares the supply voltage in relation to one or more threshold values to determine if the supply voltage is less than a minimum nominal voltage. In response to the supply voltage falling below the minimal nominal voltage, amplifier gain is reduced to maintain amplifier linearity. A second threshold may be utilized in the comparison to the supply voltage when transitioning to the original gain level to prevent oscillation. A latching may be provided to prevent gain changes during active transmit periods.

Abstract: In a portable radio transceiver, such as a mobile wireless telephone, conditions indicative of transmitter distortion (as represented by error vector magnitude (EVM)) are sensed, and transmitted RF power is adjusted in response, so as to reduce distortion and decrease EVM. The conditions can include high VSWR or a combination of high VSWR and low battery power.

Abstract: A system for pre-charging a current mirror includes a controller configured to provide a first current and an additional current to a current mirror to rapidly charge a capacitance associated with the current mirror based on a reference voltage or control signals. A power amplifier module includes at least one current minor and a controller. A capacitor is coupled to the current minor. The controller provides a bias current in an amount proportional to an input to a voltage-to-current converter. The controller receives a control signal that directs the controller to apply one of a pre-charge voltage and a nominal voltage to the voltage-to-current converter.

Abstract: In a voltage converter, a mode configuration is selected in response to a mode control signal using a switch matrix having two or more mode configurations. Each mode configuration corresponds to one of two or more output signal voltages. The output signal is compared with a reference signal to produce a direction comparison signal. The direction comparison signal is used to produce the mode control signal.

Abstract: In a mobile wireless telecommunication device, a bidirectional serial interface is used to transfer a digital representation of an analog value from a first chip associated with a power amplifier module to a second chip. In an exemplary embodiment, circuitry on the first chip receives this clock signal from the second chip during the address portion of a read operation and uses this clock signal to generate a conversion clock signal. An analog-to-digital converter (ADC) on the first chip operates in response to the conversion clock signal to convert an analog value to a digital output. Circuitry on the first chip then transfers the digital output of the ADC from the first chip to the second chip via the serial interface.

Abstract: An apparatus on a single integrated circuit (IC) die includes a multiple stage power amplifier having at least first and second stages, a multiple stage voltage regulator for providing a regulated voltage signal to the at least first and second stages of the multiple stage power amplifier, a power coupler for providing a portion of a power output of the multiple stage power amplifier to a power detector, the power detector for developing a power detect signal, and a power control loop including at least the second stage and an output stage of the multiple stage power amplifier, the power coupler, the power detector, and at least one stage of the multiple stage voltage regulator, the power control loop controlling only the second stage and the output stage of the multiple stage power amplifier.

Abstract: A radio frequency (RF) power amplification system in which a combination of a linear voltage regulator having a PFET pass device and a DC-DC converter having an NFET pass device is used to supply power to an RF power amplifier. The RF power amplifier receives power from either the linear voltage regular and its associated PFET pass device or the DC-DC converter and its NFET pass device, depending upon the condition of a mode signal.

Abstract: A low noise RF driver circuit including at least two series-coupled driver stages which receive a frequency modulated signal and an amplitude modulated signal that is applied to the supply voltage input of the driver stages, and provide a combined output signal. The RF driver circuit can be implemented in CMOS technology and integrated with other components of an RF communication subsystem, such as an RF transceiver circuit and power amplifier. Each driver stage includes a complementary pair of transistors with source degeneration resistors for linearity and gain control.

Abstract: A power amplification circuit includes a power amplifier, an RF detector, an error amplifier, a saturation detector, and an offset circuit. The power amplifier provides an amplified signal based on an input signal and a gain control signal. The RF detector provides a detection signal indicative of a logarithm of the power of the amplified signal. The error amplifier provides the gain control signal based on an amplification control signal and the detection signal. The saturation detector provides a saturation signal in response to the gain control signal differing from a reference signal by less than a first predetermined voltage. The offset circuit decreases a voltage level of the amplification control signal by up to a second predetermined voltage in response to the saturation signal and the amplification control signal differing from the detection signal by less than the second predetermined voltage.

Abstract: A power amplification circuit includes a power amplifier, an RF detector, an error amplifier, a saturation detector, and an offset circuit. The power amplifier provides an amplified signal based on an input signal and a gain control signal. The RF detector provides a detection signal indicative of a logarithm of the power of the amplified signal. The error amplifier provides the gain control signal based on an amplification control signal and the detection signal. The saturation detector provides a saturation signal in response to the gain control signal differing from a reference signal by less than a first predetermined voltage. The offset circuit decreases a voltage level of the amplification control signal by up to a second predetermined voltage in response to the saturation signal and the amplification control signal differing from the detection signal by less than the second predetermined voltage.

Abstract: An apparatus on a single integrated circuit (IC) die includes a multiple stage power amplifier having at least first and second stages, a multiple stage voltage regulator for providing a regulated voltage signal to the at least first and second stages of the multiple stage power amplifier, a power coupler for providing a portion of a power output of the multiple stage power amplifier to a power detector, the power detector for developing a power detect signal, and a power control loop including at least the second stage and an output stage of the multiple stage power amplifier, the power coupler, the power detector, and at least one stage of the multiple stage voltage regulator, the power control loop controlling only the second stage and the output stage of the multiple stage power amplifier.

Abstract: A low noise RF driver circuit including at least two series-coupled driver stages which receive a frequency modulated signal and an amplitude modulated signal that is applied to the supply voltage input of the driver stages, and provide a combined output signal. The RF driver circuit can be implemented in CMOS technology and integrated with other components of an RF communication subsystem, such as an RF transceiver circuit and power amplifier. Each driver stage includes a complementary pair of transistors with source degeneration resistors for linearity and gain control.

Abstract: Systems and methods are described for detecting and correcting saturation in a power amplification circuit. An exemplary circuit comprises a power amplifier that provides an amplified output signal based upon an input signal and a gain control signal; a power detector that provides a detector signal indicative of the amplified signal magnitude; an error amplifier that generates the gain control signal based upon a setpoint signal and the detector signal; and a saturation detector that provides a saturation detection signal indicating whether gain control signal exceeds a reference signal. In another embodiment the circuit comprises an offset generator that provides a correction to the setpoint signal in response to the saturation detection signal indicating that the gain control signal exceeds the reference signal. In still another embodiment the circuit includes an offset cutoff circuit that freezes the correction to the setpoint signal in response to the correction exceeding a threshold.

Abstract: An apparatus for sensing power amplifier current includes a system voltage source that is used to develop a reference voltage, a wire bond structure connected between the system voltage source and a power amplifier, where a sense voltage developed across the wire bond structure is indicative of a current flowing through the power amplifier, and a current source configured to compensate the reference voltage for changes in resistance of the wire bond structure due to a temperature coefficient of the wire bond structure.

Abstract: In a mobile wireless telecommunication device, a bidirectional serial interface is used to transfer a digital representation of an analog value from a first chip associated with a power amplifier module to a second chip. In an exemplary embodiment, circuitry on the first chip receives this clock signal from the second chip during the address portion of a read operation and uses this clock signal to generate a conversion clock signal. An analog-to-digital converter (ADC) on the first chip operates in response to the conversion clock signal to convert an analog value to a digital output. Circuitry on the first chip then transfers the digital output of the ADC from the first chip to the second chip via the serial interface.