Abstract: Method for ascertaining an operating range for an integrated circuit which has a plurality of system components, in which a test routine is performed for testing at least one system component from the plurality of system components, where the at least one system component is not in operation and at least one other untested system component from the plurality of system components is ready for operation when the at least one system component is tested.

Abstract: Embodiments of the invention relate generally to an apparatus, to an embedded memory, to an address decoder, to a method of reading out data and to a method of configuring a memory. In an embodiment of the invention an apparatus is provided. The apparatus may include a plurality of read-only memory (ROM) cells and an address decoder to access a ROM cell of the plurality of ROM cells, the address decoder further being fuse-programmable to divert an access to the ROM cell to a different memory cell.

Abstract: The present invention provides a data processing apparatus having at least one dedicated data processing device (10) of a first type, a central data processing device (4) for controlling dedicated data processing devices (10, 12, 14), at least one data transmission channel (16) for transmitting data between the data processing devices (4, 10, 12, 14) and a data transmission device (6) for transmitting data between the data processing devices via the at least one data transmission channel (16) in a manner dependent on data transmission parameters, the data transmission parameters which are assigned to the at least one dedicated data processing device (10) of the first type being generated by the at least one dedicated data processing device (10) of the first type.

Abstract: Embodiments of the invention relate generally to an apparatus, to an embedded memory, to an address decoder, to a method of reading out data and to a method of configuring a memory. In an embodiment of the invention an apparatus is provided. The apparatus may include a plurality of read-only memory (ROM) cells and an address decoder to access a ROM cell of the plurality of ROM cells, the address decoder further being fuse-programmable to divert an access to the ROM cell to a different memory cell.

Abstract: Method for ascertaining an operating range for an integrated circuit which has a plurality of system components, in which a test routine is performed for testing at least one system component from the plurality of system components, where the at least one system component is not in operation and at least one other untested system component from the plurality of system components is ready for operation when the at least one system component is tested.

Abstract: The present invention provides a data processing apparatus having at least one dedicated data processing device (10) of a first type, a central data processing device (4) for controlling dedicated data processing devices (10, 12, 14), at least one data transmission channel (16) for transmitting data between the data processing devices (4, 10, 12, 14) and a data transmission device (6) for transmitting data between the data processing devices via the at least one data transmission channel (16) in a manner dependent on data transmission parameters, the data transmission parameters which are assigned to the at least one dedicated data processing device (10) of the first type being generated by the at least one dedicated data processing device (10) of the first type.

Abstract: The invention relates to a processor/memory system having at least one processor, a memory unit, and at least one memory control unit for controlling accesses from the at least one processor to the memory unit. The system also includes a hardware configuration unit operable to configure the at least one memory control unit when the at least one memory control unit changes from a low-power operating mode to a normal-power operating mode.

Abstract: A timing device for generating and outputting a plurality of signal edges by changing signal statuses at predeterminable times. The timing device includes a cyclically addressable memory in which a plurality of time events are stored. Each time event is assigned a time value, which corresponds to a predetermined time, and a plurality of predetermined signal statuses. The timing device further includes a comparator, which compares the current count of a counter to the time value of a time event, which has just been acquired from memory. Given a match, the next time event is read from the memory. The timing device also includes an output device which outputs the predetermined signal statuses. With the timing device it is possible to freely program periodically recurring time indications by allocating memory accordingly.

Abstract: A method for adding information to an object, by preparing the object to receive an extension object and attaching, during run-time, the extension object to the object, wherein the extension object includes the information to be added to the object. A system comprising an object, a primary interface including methods which allow information to be added to the object during run-time, wherein the object and the primary interface are compiled with the system and an extension object including information to be added to the object, wherein the extension object is attached to the object during run-time.