Abstract: The disclosure relates in part to methods and compositions for detecting targets in a sample. Such methods and compositions can be useful for laboratory, research, and diagnostic purposes.

Abstract: Provided for example is a system and method for real-time monitoring or controlling wastewater or sludge dewatering or thickening processes. The system and method can also enable operators to remotely monitor their own system off-site.

Abstract: The invention relates to a method for cleaning a sensor in a wastewater monitoring arrangement comprising at least one sensor with a sensor surface, such as an optical sensor with a window, lens, or the like. In the monitoring arrangement, during a normal operation mode, a sample flow of wastewater is arranged to flow past the sensor surface and the sensor is arranged to provide measurement values that describe a quality parameter of the wastewater. The method comprising steps of: starting a sensor cleaning cycle by discontinuing the sample flow; starting a cleaning liquid flow; arranging the cleaning liquid flow towards the sensor surface; mechanically cleaning the sensor surface by an automatic cleaning device; discontinuing the cleaning liquid flow after a predetermined cleaning time and ending the cleaning cycle; and starting the wastewater flow again.

Abstract: The present invention relates to a system (17) for real-time monitoring and/or controlling wastewater or sludge dewatering and/or thickening processes, said system (17) comprising a wastewater piping (13) comprising a wastewater inlet (1) and a concentrated wastewater outlet (18); at least one dewatering or thickening device (14), attached to said wastewater piping (13) between the inlet (1) and the outlet (18); at least one total solids measurement device (2, 8, 11), attached to said wastewater piping (13); at least one total suspended solids measurement device (3, 7, 10), attached to said wastewater piping (13) or a fluid outlet (9) of the dewatering or thickening device (14); an inorganic coagulant container (4) connected to said wastewater piping (13); a feeding valve (5) to control a flow of inorganic coagulant from said inorganic coagulant container (4) to said wastewater piping (13); and a control unit (15); wherein the flow of inorganic coagulant is adapted to be controlled to uphold at least a predet

Abstract: A method of controlling addition rate of an odor control chemical to a wastewater line by adding odor control chemical to the wastewater. The method includes measuring a level of dissolved sulfides in the wastewater line using a sulfide probe placed in said wastewater line, transferring data on the level of dissolved sulfides to a computing unit, determining a required odor control chemical addition rate in said computing unit based on said level of dissolved sulfides, and adding the odor control chemical at said required addition rate. The method allows for accurate on-line control of the level of H2S in the wastewater line.

Abstract: The invention describes a method and system for controlling the addition rate of a contaminant control chemical to a water or wastewater line. The level of hexavalent chromium as a contaminant in the water or wastewater is measured using a spectro-photometric probe placed in the line. Data representative of the level of measured hexavalent chromium content is read into a computing unit, which determines a required contaminant control chemical addition rate based on said level of hexavalent chromium content. The contaminant control chemical is then added at the required addition rate to reduce the amount of hexavalent chromium to a predetermined level.

Abstract: As disclosed herein, the present invention provides for kits and a composition for diagnosis, prognosis, drug discovery, drug development, and patient stratification. The kits can comprise a plurality of binding elements for cell surface markers, and a plurality of binding elements for state-specific intracellular markers. The kits can further comprise a plurality of modulators directed for the particular cell function or signaling pathways. The kits can further include fixatives, permeabilizing agent, buffers, containers, instructions, and software for data analysis/compilation.

Abstract: As disclosed herein, the present invention provides for kits and a composition for diagnosis, prognosis, drug discovery, drug development, and patient stratification. The kits can comprise a plurality of binding elements for cell surface markers, and a plurality of binding elements for state-specific intracellular markers. The kits can further comprise a plurality of modulators directed for the particular cell function or signaling pathways. The kits can further include fixatives, permeabilizing agent, buffers, containers, instructions, and software for data analysis/compilation.

Abstract: As disclosed herein, the present invention provides for kits and a composition for diagnosis, prognosis, drug discovery, drug development, and patient stratification. The kits can comprise a plurality of binding elements for cell surface markers, and a plurality of binding elements for state-specific intracellular markers. The kits can further comprise a plurality of modulators directed for the particular cell function or signaling pathways. The kits can further include fixatives, permeabilizing agent, buffers, containers, instructions, and software for data analysis/compilation.

Abstract: A method for controlling application of an erasure mode of an error correction code (ECC) algorithm in a memory subsystem includes detecting errors in cache lines retrieved from the memory subsystem using the ECC algorithm. The method also analyzes the errors to detect a repeated bit pattern of data corruption within the cache lines, correlates the detected repeated bit pattern of data corruption to one of a plurality of domains of the memory subsystem, and applies the ECC algorithm to erase bits associated with the detected repeated bit pattern from cache lines retrieved from the correlated domain of the memory subsystem.

Abstract: A system utilizing an erasure mode in an error correction code algorithm is described that includes non-volatile memory storing a page deallocation table. A memory controller stores and retrieves data from a memory subsystem, and uses an error correction code algorithm to correct data corruption in retrieved data. An error analysis algorithm executed in a processor records instances of data corruption in the page deallocation tables and deallocates memory regions associated with multiple occurrences of data corruption at single bit locations. The error analysis algorithm further causes the memory controller to apply an erasure mode of the error correction code algorithm upon detection of a repeated pattern of data corruption across different addresses of the memory subsystem, and removes entries in the page deallocation table that correspond to data corruption addressed by application of the erasure mode.

Abstract: In one embodiment, a computer readable medium comprises code for recording occurrences of data corruption in data retrieved from a memory subsystem, code for determining whether bit locations within the memory subsystem are associated with multiple occurrences of data corruption, code for deallocating, in response to the code for determining, memory regions containing bit locations associated with multiple occurrences of data corruption, code for analyzing patterns of data corruption repeated across multiple addresses of the memory subsystem, and code for controlling application of an error correction code (ECC) algorithm by the memory subsystem to erase bits associated with a repeated bit pattern, detected by the code for analyzing, from data retrieved from the memory subsystem.

Abstract: One embodiment is a method of dynamically adjusting a rate at which a dynamic random access memory (“DRAM”) module is refreshed in a computer system. The method comprises monitoring a plurality of system conditions; detecting a change in at least one of the monitored system conditions; responsive to the detection, determining an optimum refresh rate for a current state of the computer system; and setting the refresh rate to the determined optimum refresh rate.

Abstract: In one embodiment, a system comprises non-volatile memory storing a page deallocation table (PDT), a memory controller for storing and retrieving data from a memory subsystem, the memory controller using an error correction code (ECC) algorithm to correct data corruption in retrieved data, a processor for executing an error analysis algorithm, the error analysis algorithm recording instances of data corruption in the PDT, deallocating memory regions associated with multiple occurrences of data corruption at single bit locations, the error analysis algorithm causing the memory controller to apply an erasure mode of the ECC algorithm upon detection of a repeated pattern of data corruption across different addresses of the memory subsystem, and removing entries in the PDT that correspond to data corruption addressed by application of the erasure mode.

Abstract: In one embodiment of the invention, a computer readable medium, comprising executable instructions for controlling application of an error correction code (ECC) algorithm in a memory subsystem, comprises code for recording occurrences of data corruption in data retrieved from the memory subsystem, code for analyzing the occurrences of data corruption to detect a repeated bit pattern of data corruption across different addresses of the memory subsystem, and code for controlling application of the ECC algorithm to erase bits associated with a repeated bit pattern, detected by the code for analyzing, from data retrieved from the memory subsystem.

Abstract: In one embodiment, a computer readable medium comprises code for recording occurrences of data corruption in data retrieved from a memory subsystem, code for determining whether bit locations within the memory subsystem are associated with multiple occurrences of data corruption, code for deallocating, in response to the code for determining, memory regions containing bit locations associated with multiple occurrences of data corruption, code for analyzing patterns of data corruption repeated across multiple addresses of the memory subsystem, and code for controlling application of an error correction code (ECC) algorithm by the memory subsystem to erase bits associated with a repeated bit pattern, detected by the code for analyzing, from data retrieved from the memory subsystem.

Abstract: A system and method is disclosed for managing a plurality of hardware properties in a component-based system comprising representing the plurality of hardware properties using a data-descriptive meta-language, and making the hardware properties available to client devices according to the data-descriptive meta-language.