Patents by Inventor David Su

David Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030155976
    Abstract: The present invention provides a breakdown resistant transistor structure for amplifying communication signals. This structure includes a first NMOS transistor having a source connected to ground and a first gate for receiving the input radio frequency signal. The first gate is disposed above a first insulator and the first NMOS transistor having a first transconductance and a first breakdown voltage associated therewith. Also included is a second NMOS transistor having a source connected to the drain of the first NMOS transistor, a gate connected to the reference DC voltage, and a drain that provides the output for the amplified radio signal, the load being disposed between the reference DC voltage and the drain of the second NMOS transistor. The second gate is disposed above a second insulator, the second NMOS transistor has a second transconductance and a second breakdown voltage associated therewith, and the second insulator may be thicker than the first insulator.
    Type: Application
    Filed: January 7, 2003
    Publication date: August 21, 2003
    Inventors: David J. Weber, Patrick Yue, David Su
  • Patent number: 6504433
    Abstract: The present invention provides a breakdown resistant transistor structure for amplifying communication signals. This structure includes a first NMOS transistor having a source connected to ground and a first gate for receiving the input radio frequency signal. The first gate is disposed above a first insulator and the first NMOS transistor having a first transconductance and a first breakdown voltage associated therewith. Also included is a second NMOS transistor having a source connected to the drain of the first NMOS transistor, a gate connected to the reference DC voltage, and a drain that provides the output for the amplified radio signal, the load being disposed between the reference DC voltage and the drain of the second NMOS transistor. The second gate is disposed above a second insulator, the second NMOS transistor has a second transconductance and a second breakdown voltage associated therewith, and the second insulator may be thicker than the first insulator.
    Type: Grant
    Filed: September 15, 2000
    Date of Patent: January 7, 2003
    Assignee: Atheros Communications, Inc.
    Inventors: David J. Weber, Patrick Yue, David Su
  • Patent number: 6504431
    Abstract: The present invention provides a breakdown resistant transistor structure for amplifying communication signals. This structure includes a first NMOS transistor having a source connected to ground and a first gate for receiving the input radio frequency signal. The first gate is disposed above a first insulator and the first NMOS transistor having a first transconductance and a first breakdown voltage associated therewith. Also included is a second NMOS transistor having a source connected to the drain of the first NMOS transistor, a gate connected to the reference DC voltage, and a drain that provides the output for the amplified radio signal, the load being disposed between the reference DC voltage and the drain of the second NMOS transistor. The second gate is disposed above a second insulator, the second NMOS transistor has a second transconductance and a second breakdown voltage associated therewith, and the second insulator may be thicker than the first insulator.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: January 7, 2003
    Assignee: Atheros Communications, Inc.
    Inventors: David J. Weber, Patrick Yue, David Su
  • Patent number: 6483188
    Abstract: A radio-frequency (RF) integrated circuit is described. In one embodiment, the IC comprises multiple metal layers forming multiple transistors on a non-epitaxial substrate. The transistors are step and mirror symmetric. Also, the RF signal lines are on a top metal layer above all other metal layers and the power and ground planes are on a bottom metal layer below all other metal layers. The top and bottom metal layers are separated by a shield that extends beyond the RF signal lines by a distance that is at least the same distance that the shield is away from the RF lines. Low frequency signals are on signal lines below the top metal layer.
    Type: Grant
    Filed: May 15, 2000
    Date of Patent: November 19, 2002
    Assignee: Atheros Communications, Inc.
    Inventors: Chik Patrick Yue, Masoud Zargari, David Su
  • Publication number: 20020105380
    Abstract: The present invention provides a breakdown resistant transistor structure for amplifying communication signals. This structure includes a first NMOS transistor having a source connected to ground and a first gate for receiving the input radio frequency signal. The first gate is disposed above a first insulator and the first NMOS transistor having a first transconductance and a first breakdown voltage associated therewith. Also included is a second NMOS transistor having a source connected to the drain of the first NMOS transistor, a gate connected to the reference DC voltage, and a drain that provides the output for the amplified radio signal, the load being disposed between the reference DC voltage and the drain of the second NMOS transistor. The second gate is disposed above a second insulator, the second NMOS transistor has a second transconductance and a second breakdown voltage associated therewith, and the second insulator may be thicker than the first insulator.
    Type: Application
    Filed: March 26, 2002
    Publication date: August 8, 2002
    Applicant: ATHEROS COMMUNICATIONS, INC.
    Inventors: David J. Weber, Patrick Yue, David Su
  • Patent number: 6272322
    Abstract: A calibration method and apparatus are described. In one embodiment, the method includes a pair of transceivers performing a loop back test to determine a relationship between transmit and receive gain for each transceiver. A path loss between the first transceiver and a second transceiver is computed. The computation is made by transmitting a pair of signals in opposite directions between the first and second transceivers to determine a relationship between transmit path gain of the first transceiver and receive path gain of the second transceiver and a relationship between the transmit path gain of the second transceiver and receive path of the first transceiver. The transmit and receive path gains are generated for the first transceivers based on the path loss and the relationship.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: August 7, 2001
    Assignee: Atheros Communications, Inc.
    Inventor: David Su
  • Patent number: 6163267
    Abstract: The invention relates to a device for measuring noise comprising a sensor circuit having at least two sensors, an ambient noise eliminating circuit and a signal processing circuit. All the sensors are set to detect the ambient or background noise, however the source noise is positioned for detection by one of the sensors. The output of the sensor circuit is connected to the input of the ambient noise eliminating circuit where the ambient noise is eliminated from the noise signal leaving only a signal of the noise source. The signal processing circuit receives the signal of the measured noise, which is rectified and amplified, and then processed in the comparator circuit to determine whether the noise level is acceptable or not. The result is displayed through the display circuit comprising a plurality of LEDs.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: December 19, 2000
    Assignee: Sunonwealth Electric Machine Industry Co., Ltd.
    Inventor: David Su
  • Patent number: 5973556
    Abstract: A delta-modulated magnitude amplifier is used to amplify the magnitude component of an RF power amplifier that employs envelope elimination and restoration. The delta-modulated amplifier introduces a smaller amount of non-linearity than traditional approaches, which are based upon pulse-width modulation. The disclosed technique can be implemented using switched-capacitor circuits in a standard MOS technology with only two external components, i.e., an inductor and a capacitor. Thus, the disclosed technique allows the implementation of an efficient and yet linear RF power amplifier using low-cost MOS technology.
    Type: Grant
    Filed: September 18, 1998
    Date of Patent: October 26, 1999
    Assignee: Hewlett-Packard Company
    Inventor: David Su
  • Patent number: 5847602
    Abstract: A delta-modulated magnitude amplifier is used to amplify the magnitude component of an RF power amplifier that employs envelope elimination and restoration. The delta-modulated amplifier introduces a smaller amount of non-linearity than traditional approaches, which are based upon pulse-width modulation. The disclosed technique can be implemented using switched-capacitor circuits in a standard MOS technology with only two external components, i.e., an inductor and a capacitor. Thus, the disclosed technique allows the implementation of an efficient and yet linear RF power amplifier using low-cost MOS technology.
    Type: Grant
    Filed: March 3, 1997
    Date of Patent: December 8, 1998
    Assignee: Hewlett-Packard Company
    Inventor: David Su
  • Patent number: D440557
    Type: Grant
    Filed: July 21, 2000
    Date of Patent: April 17, 2001
    Inventor: David Su