Patents by Inventor David T. CHIN

David T. CHIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8650748
    Abstract: A method of fabricating chip carriers suitable for use in packaging integrated circuits and other electronic, electro-mechanical and opto-electronic devices is described. In general, a number of wires (or wires and rods) are arranged in parallel in a wiring fixture. After the wires are positioned, they are encapsulated to form an encapsulated wiring block. The wiring block is then sliced to form a number of discrete panels. Preferably, the various wires are geometrically positioned such that each resulting panel has a large number of device areas defined therein. The encapsulant in each panel effectively forms a substrate and the wire segments in each panel form conductive vias that extend through the substrate. The resulting panels/chip carriers can then be used in a wide variety of packaging applications.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: February 18, 2014
    Assignee: National Semiconductor Corporation
    Inventors: Artur Darbinyan, David T. Chin, Kurt E. Sincerbox
  • Publication number: 20120285730
    Abstract: A method of fabricating chip carriers suitable for use in packaging integrated circuits and other electronic, electro-mechanical and opto-electronic devices is described. In general, a number of wires (or wires and rods) are arranged in parallel in a wiring fixture. After the wires are positioned, they are encapsulated to form an encapsulated wiring block. The wiring block is then sliced to form a number of discrete panels. Preferably, the various wires are geometrically positioned such that each resulting panel has a large number of device areas defined therein. The encapsulant in each panel effectively forms a substrate and the wire segments in each panel form conductive vias that extend through the substrate. The resulting panels/chip carriers can then be used in a wide variety of packaging applications.
    Type: Application
    Filed: May 12, 2011
    Publication date: November 15, 2012
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Artur DARBINYAN, David T. CHIN, Kurt E. SINCERBOX
  • Publication number: 20120057313
    Abstract: Methods and arrangements for packaging system level electronics are described. In one aspect, an external skin of the package is formed from isolation paper. In some embodiments, the isolation paper is formed into a box. A printed circuit board is placed within the isolation paper skin and is substantially completely surrounded by a potting material that substantially completely fills the skin. The potting material is cured to solidify the potting material within the isolation paper box and to adhere the potting material to the isolation paper such that the isolation paper forms a skin for a brick of potting material that encapsulates the printed circuit board. The isolation paper skin includes at least one opening that permits an interconnect to be exposed through the skin. With this arrangement, a packaged electronics device is provided and the isolation paper forms the exposed outer surface of the packaged electronics device.
    Type: Application
    Filed: September 3, 2010
    Publication date: March 8, 2012
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Artur DARBINYAN, Kurt E. SINCERBOX, David T. CHIN