Patents by Inventor David Thomas REID

David Thomas REID has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11979070
    Abstract: An insulation system and method are disclosed for insulating formed coils of electrical machines, such as motors and generators. The system includes strand/turn insulation that may include one or more layers of different materials, depending upon the dielectric requirements. A ground wall insulation is applied over the group of turns. The coil may be sized in a slot cell section. Additional insulation layers are provided, including a slot corona suppression insulation that extends just beyond stator slots, a voltage grading layer, and an armor layer. The resulting system is highly adaptable to different machine designs and ratings, and affords superior resistance to degradation.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: May 7, 2024
    Assignee: Integrated Power Services LLC
    Inventors: Ray Thomas Reid, Mark D. Nikrandt, Donald Dolence, David N. Scherer
  • Patent number: 10747916
    Abstract: A method for generating semiconductor device model parameters includes receiving semiconductor device performance data of statistical instances of semiconductor devices, for a plurality of coordinates in a process space with dimensions of process-dependent device parameters Model parameters are extracted to produce individual model instances, each corresponding to the respective statistical instances for the coordinates in the process space. Statistics of the extracted model parameters are modeled by processing the individual model instances to determine, for each coordinate in the process space, moments describing non-normal marginal distributions of the extracted model parameters and correlations between the extracted model parameters. Semiconductor device model parameters are generated for use in simulating a circuit using the determined moments and the determined correlations, for a selected coordinate in the process space.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: August 18, 2020
    Assignee: Synopsys, Inc.
    Inventor: David Thomas Reid
  • Patent number: 10713405
    Abstract: A method for generating semiconductor device model parameters includes receiving semiconductor device performance data of statistical instances of semiconductor devices, for a plurality of areal trapped charge densities Model parameters are extracted to produce individual model instances, each corresponding to the respective statistical instances for the areal trapped charge densities. Statistics of the extracted model parameters are modeled by processing the individual model instances to determine, for each areal trapped charge density, moments describing non-normal marginal distributions of the extracted model parameters and correlations between the extracted model parameters. Semiconductor device model parameters are generated for use in simulating a circuit using the determined moments and the determined correlations, for a selected areal trapped charge density.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: July 14, 2020
    Assignee: SYNOPSYS, INC.
    Inventor: David Thomas Reid
  • Publication number: 20160378717
    Abstract: In one embodiment, a method for generating semiconductor device model parameters includes the steps: (a) receiving semiconductor device performance data of statistical instances of semiconductor devices, for a plurality of coordinates in a process space with dimensions of process-dependent device parameters; (b) extracting model parameters to produce a plurality of individual model instances each corresponding to the respective statistical instances for the coordinates in process space; (c) modeling statistics of the extracted model parameters by processing the individual model instances to determine, for each coordinate in process space: moments describing non-normal marginal distributions of the extracted model parameters and correlations between the extracted model parameters; and (d) generating semiconductor device model SPICE parameters using the determined moments and the determined correlations, for a selected coordinate in process space.
    Type: Application
    Filed: May 9, 2016
    Publication date: December 29, 2016
    Inventor: David Thomas REID
  • Publication number: 20160342719
    Abstract: In one embodiment, a method for generating semiconductor device model parameters includes the steps: (a) receiving semiconductor device performance data of statistical instances of semiconductor devices, for a plurality of areal trapped charge densities; (b) extracting model parameters to produce a plurality of individual model instances each corresponding to the respective statistical instances for the areal trapped charge densities; (c) modeling statistics of the extracted model parameters by processing the individual model instances to determine, for each areal trapped charge density: moments describing non-normal marginal distributions of the extracted model parameters and correlations between the extracted model parameters; and (d) generating semiconductor device model SPICE parameters using the determined moments and the determined correlations, for a selected areal trapped charge density.
    Type: Application
    Filed: May 9, 2016
    Publication date: November 24, 2016
    Inventor: David Thomas REID