Abstract: The invention relates to an intracorporeal probe (10), for example preferably for examining hollow organs or natural or artificially created body cavities in the human or animal body, the probe (10) being designed in the form of a capsule that can be introduced into the body without external connecting elements, comprising an elongate housing (16) and an image pickup unit (26) inside the housing (16) that is designed for optically recording a region (pickup region) outside the probe (10). The image pickup unit (26) is held in a fashion capable of moving inside the housing (16) in order to vary the pickup region by means of such a movement (FIG. 1).

Abstract: Electronic component including a ternary content-addressable memory component, configured to compare the input data items with a set of pre-recorded reference data words; the memory component incorporates a matrix of elementary cells arranged in lines and columns; each line incorporates cells in each of which is recorded one bit of one of the reference data words; the cells of a given column are dedicated to the comparison of the same bit of the input data word; each cell incorporates: two memory points storing the data representing the reference data bit; a comparison circuit connected to the memory points, with a comparison point of which the potential represents the comparison if the input data bit and the data stored in the memory points, and also incorporating a common comparison circuit to which are connected the comparison circuits of all or part of the cells of a given column; the comparison circuit incorporates terminals to which the bit from the input data word and its complement are applied.

Abstract: Electronic component including a ternary content-addressable memory component, configured to compare the input data items with a set of pre-recorded reference data words; the memory component incorporates a matrix of elementary cells arranged in lines and columns; each line incorporates cells in each of which is recorded one bit of one of the reference data words; the cells of a given column are dedicated to the comparison of the same bit of the input data word; each cell incorporates: two memory points storing the data representing the reference data bit; a comparison circuit connected to the memory points, with a comparison point of which the potential represents the comparison if the input data bit and the data stored in the memory points, and also incorporating a common comparison circuit to which are connected the comparison circuits of all or part of the cells of a given column; the comparison circuit incorporates terminals to which the bit from the input data word and its complement are applied.

Abstract: A ternary content-addressable cell is configured to compare an input binary data item present on an input terminal with two reference binary data items, and to output a match signal on a match line. The cell includes: a first storage circuit (storing a potential representing the first reference binary data item) and a second storage cell (storing a potential representing the second reference binary data item). A comparison circuit is connected to the first and second storage circuits and to the input terminal SL. A comparison node presents a potential representing the comparison of the input binary data item with the first and second reference data items. The comparison node is connected to an output stage, and the output stage is connected to the match line. The signal on the match line is based on the potential of the comparison node.

Abstract: A volatile memory including volatile memory cells adapted to the performing of data write and read operations. The memory cells are arranged in rows and in columns and, further, are distributed in separate groups of memory cells for each row. The memory includes a first memory cell selection circuit configured to perform write operations and a second memory cell selection circuit, different from the first circuit, configured to perform read operations. The first circuit is capable of selecting, for each row, memory cells from one of the group of memory cells for a write operation. The second circuit is capable of selecting, for each row, memory cells from one of the groups of memory cells for a read operation.

Abstract: A measuring circuit is provided for a memory integrated within a semiconductor device. The measuring circuit includes initializing means and an oscillating loop. The initializing means loadings two complementary values into at least two locations of the memory. The two locations are addressed by a first address and a second address. The oscillating loop comprises a logic circuit for alternatively generating the first address and the second address from data read from the memory so as to successively read data from the first and second memory locations to produce an oscillating signal that has a frequency that depends on internal parameters of the memory. Also provided is a method for qualifying a memory by initializing the memory by loading two complementary values into two locations, and generating an oscillating signal with a frequency that is dependent on internal parameters of the memory.

Abstract: The invention relates to an intracorporeal probe (10), for example preferably for examining hollow organs or natural or artificially created body cavities in the human or animal body, the probe (10) being designed in the form of a capsule that can be introduced into the body without external connecting elements, comprising an elongate housing (16) and an image pickup unit (26) inside the housing (16) that is designed for optically recording a region (pickup region) outside the probe (10). The image pickup unit (26) is held in a fashion capable of moving inside the housing (16) in order to vary the pickup region by means of such a movement (FIG. 1).

Abstract: A measuring circuit is provided for a memory integrated within a semiconductor device. The measuring circuit includes initializing means and an oscillating loop. The initializing means loadings two complementary values into at least two locations of the memory. The two locations are addressed by a first address and a second address. The oscillating loop comprises a logic circuit for alternatively generating the first address and the second address from data read from the memory so as to successively read data from the first and second memory locations to produce an oscillating signal that has a frequency that depends on internal parameters of the memory. Also provided is a method for qualifying a memory by initializing the memory by loading two complementary values into two locations, and generating an oscillating signal with a frequency that is dependent on internal parameters of the memory.

Abstract: A memory cell (1), includes a flip-flop (2) that has additional read/write terminals; a 1-bit write line (wb11); a first transistor (T4) switching between the 1-bit write line and the terminal, its gate being connected to a word selection line (W11); a 0-bit write line (wb10); a second transistor (T3) switching between the 0-bit write line and the terminal, its gate being connected to a word selection line (W12); a bit read line (b1r); and read transistors (T1, T2), with one of their gates being connected to a read/write terminal and the other being connected to a word selection line.

Abstract: A ROM-type memory is provided that includes a matrix of memory cells made up of rows and columns, with each row allowing storage of a page of MUX words of N bits. An address decoder decodes addresses in order to extract the page to be read. At the output of the matrix, N multiplexers are each coupled to the columns that correspond to one of the bits of the output stage. An N-bit output stage includes at least one inverter, with each of the inverters being connected to the output of one of the multiplexers so as to restore inverted values of information to be stored to correct values. The inverted values are stored in all of the memory cells of all of the columns coupled to the one multiplexer. Storing the inverted values makes it possible to store less “0” values within the matrix and further makes LVS testing of the ROM memory considerably easier. Also provided is a method for sequentially checking groups of memory cells.

Abstract: To detect the completion of an operation for writing of a data bit into a memory cell, during the write operation, a data bit written in the memory cell is stored in a dummy memory cell and a change of state of the internal nodes of the dummy memory cell is detected upon the completion of the write operation. The data bit is stored in the dummy memory cell in a storage device that has a lower capacitance relative to the capacitance of the memory cell.

Abstract: A memory cell (1), includes: a flip-flop (2) that has additional read/write terminals; a 1-bit write line (wb11); a first transistor (T4) switching between the 1-bit write line and the terminal, its gate being connected to a word selection line (W11); a 0-bit write line (wb10); a second transistor (T3) switching between the 0-bit write line and the terminal, its gate being connected to a word selection line (W12); a bit read line (b1r); and read transistors (T1, T2), with one of their gates being connected to a read/write terminal and the other being connected to a word selection line. The invention particularly allows the surface area and complexity of a memory cell to be reduced.

Abstract: A ROM-type memory is provided that includes a matrix of memory cells made up of rows and columns, with each row allowing storage of a page of MUX words of N bits. An address decoder decodes addresses in order to extract the page to be read. At the output of the matrix, N multiplexers are each coupled to the columns that correspond to one of the bits of the output stage. An N-bit output stage includes at least one inverter, with each of the inverters being connected to the output of one of the multiplexers so as to restore inverted values of information to be stored to correct values. The inverted values are stored in all of the memory cells of all of the columns coupled to the one multiplexer. Storing the inverted values makes it possible to store less “0” values within the matrix and further makes LVS testing of the ROM memory considerably easier. Also provided is a method for sequentially checking groups of memory cells.