Abstract: A SLDRAM System is provided with a plurality of in-circuit, calibratable memory modules and a memory controller for issuing unicast and multicast command packets to the memory modules. Command packets are transmitted over a unidirectional command link that includes a complementary pair of command clock lines, a command FLAG line and a plurality of noncomplemented command bit lines. Each of the command clock lines, command bit lines and the FLAG line is a SLIO transmission line. Data transfer operations are carried out in response to the command packets over one or more bidirectional data links that each includes two complementary pairs of data clock lines, and a plurality of noncomplemented data bit lines. Each of the data clock lines and the data bit lines is a SLIO transmission line. Each SLIO transmission line is single-end terminated and preferably tapped into by way of stub resistors.

Abstract: Both small frames and large frames of data are transmitted from a producer device to a consumer device over an IEEE 1394 serial data bus. The small frames of data are preferably transmitted to a small frame buffer associated with a plug at the consumer device. Each transfer of a small frame generates an interrupt at the consumer device when the transfer is complete. For the transfer of large frames of data, the consumer device programs an array of page table entries into the plug control register of the producer device, prior to a transfer of a large frame of data. Each of the page table entries includes a starting address of a memory page at the consumer device to which data can be written. Together, these memory pages specified by the page table entries form a large frame buffer at the consumer device for receiving a large frame of data from the producer device. Preferably, the array of page table entries can be updated by the consumer device, as appropriate, between frame transfers.

Abstract: A system and method for delivering data packets in an electronic interconnect comprises a talker device that transmits one or more data packets over a transmission path to a listener device through one or more bus bridges that each couple adjacent busses in the electronic interconnect. Each data packet includes a time stamp that indicates when the corresponding data packet is scheduled for presentation to the listener device. An initial bus bridge preferably creates a marker packet that is propagated through the transmission path to record delay information corresponding to delay elements such as the intervening bus bridges. A final bus bridge may then utilize the delay information from the marker packet to update the time stamps of the data packets to thereby incorporate the total propagation delay of the transmission path.

Abstract: A method and system for purging translation lookaside buffers (TLB) of a computer system are described. Directed write transactions can be used to avoid deadlock and avoid the need for additional bridge buffers. Broadcast emulation can be achieved by linking the nodes in a doubly-linked list and having neighboring nodes notify each other of changes in TLB entries.

Abstract: A method and system for ordering an interconnect topology to form a ring structure, the topology comprising a number of nodes, are described. In one embodiment, a self identifier for each of the nodes is determined. Further, the self identifier is mapped to a ring identifier for each node. In addition, each node computes the ring identifier of one of its port-connected nodes as its topologically adjacent neighbor identifier.

Abstract: A method and system for purging translation lookaside buffers (TLB) of a computer system are described. Directed write transactions can be used to avoid deadlock and avoid the need for additional bridge buffers. Broadcast emulation can be achieved by linking the nodes in a doubly-linked list and having neighboring nodes notify each other of changes in TLB entries.

Abstract: In a mixed-protocol multiple-processor cache coherence computer system one processor may support read-only and read-write lists while another processor may support only read-write lists. Data copied to a cache is called a cache line while a copy of the same data remaining in memory is called a memory line. A memory line is stale when its associated cache line has been modified. The main memory of the system always points to the processor at the head of each list and includes indications of fresh and stale memory line states. The present invention deletes the head entry of a read-only cache-sharing list where the head entry supports read-only operations and the next-list entry supports only read-write operations. The head of the list informs the next-list entry that the next-list entry is about to become the head of the list. The main memory then repositions its head-pointer to the next-list entry and changes the memory state from fresh to stale.

Abstract: A method of address management in a net having a plurality of buses linked by a plurality of bus bridges where the net has only one branch bus with multiple bus bridges. A local identification address is assigned to each node on a branch bus and a bus number is assigned to each bus other than the branch bus. The bus number includes a common base and the local identification address for the node having a portal that connects to that bus.

Abstract: A memory circuit with glitch-less transfer of timing information. In one embodiment, the invention is a memory circuit including a controller, multiple loads, a command link communicatively coupling the controller and the loads and a data link. The data link includes multiple data clocks and communicatively couples the controller and the multiple loads. In another embodiment, the invention transfers data between a memory controller and a RAM by coupling the controller and the RAM using a data bus and multiple clock lines. The invention transfers a read/write command from the controller to the RAM and then transfers data associated with the read/write command, clocking the data using one of the clock lines.

Abstract: A computer memory device featuring a high-bandwidth memory interface to transfer information between a controller and the memory cells of a memory modules. Bifurcated communication buses is provided to take advantage of the interface. One of the bifurcated communication busses is dedicated to data information transfer, dataLink, between the controller and the memory modules, with the remaining bus, commandLink, being dedicated to command/address information transfer therebetween. This facilitates communication between the controller and the memory modules using information packets, bifurcated into data packets and command/address packets. To that end, the interface circuitry includes encoded chip select techniques that employs slaveId comparison logic, a plurality of control registers and delay registers to regulate the synchronization of communication transfers over the commandLink and the dataLink, as well as a queue register in which the packets are temporarily stored.

Abstract: A method and system for providing cyclic redundancy check (CRC) functions within a ringlet-type interconnect of a computer system are described. By time multiplexing CRC checking and generating functions, the number of CRC units can be reduced.

Abstract: A system for implementing indivisible command execution in an AV/C home audio video network of connected network devices. A network bus operable for conveying commands among a plurality of coupled devices is coupled to each of the devices. A controller device is coupled to the network bus operable for generating a command sequence, the command sequence including a plurality of AV/C commands. A target device is coupled to the network bus, the target device operable for implementing AV/C operations by receiving and executing the command sequence. The target device is configured to identify the command sequence received from the controller via the network bus by reading a group tag field and a command status included in each AV/C command.

Abstract: A system and method for avoiding starvation and deadlocks in a split-response-bus multiprocessor computer system. The multiprocessor computer system includes a first node and a second node coupled to the a split-response bus, wherein the first and second nodes communicate by passing request packets over the split-response bus. The method and system includes providing precedence information in the request packets, and then using the precedence information when receiving the request packets to determine which request packets to process and which request packets to reject when a conflict occurs.

Abstract: A system for converting between the states of fresh and owned in a multi-processor computer system comprises a memory line with a structure including a first field for storing a memory state, a second field for storing an address, and a third field for storing data. Each of the cache lines for processors in the system includes a plurality of data fields including one for storing the cache line state, one for storing a forward pointer, one for storing a backward pointer, and one for storing data. A method is also provided for automatically washing memory lines. The system is advantageous because it allows the data to be transferred immediately when it is available, rather than requiring the next cache-line owner to poll until the data is available. Still more particularly, the present invention provides a method of reliably converting an owned data line from stale to fresh when read fresh accesses are being performed, while correctly leaving the line in an owned state if additional read owned access occur.

Abstract: A system and method for coordinating the transmission and receipt of large data blocks as a series of smaller burst transfers through an intermediate interconnect coupling a pair of devices. A device receiving a transaction request ("initiator") specifies the data block size of the requested transaction to the other device ("target"). The target response will indicate that it is committed to the transaction, that it does not support requested transactions of the specified data block size, or that it currently lacks the buffer capacity to commit to the requested transaction. In the first instance, the initiator and target exchange the data block through the interconnect as a series of burst transfers until all data has been transferred, at which time the initiator (for read transactions) or the target (for write transactions) forwards the transferred data as a data block of the specified size.

Abstract: A system and method for avoiding starvation and deadlocks in a split-response-bus multiprocessor computer system. The multiprocessor computer system includes a first node and a second node coupled to the a split-response bus, wherein the first and second nodes communicate by passing request packets over the split-response bus. The method and system includes providing precedence information in the request packets, and then using the precedence information when receiving the request packets to determine which request packets to process and which request packets to reject when a conflict occurs.

Abstract: A method and system for providing arbitration within a ringlet-type interconnect of a computer system are described. By providing different arbitration values as part of out-of-band information and introducing asymmetry at a scrubber node, fair allocation of interconnect bandwidth is achieved. The number of arbitration values can be extended from a basic set to provide additional functionality to handle specialized traffic situations.

Abstract: A system for controlling memory accesses in a memory device in a multi-processor computer system comprises a memory controller and a data storage. The data storage comprises a plurality of memory lines. Each memory line has a check field for storing a GONE code that indicates that the data is held in a cache, a g bit field for storing a G bit for confirming the code in the check field, a tag field for storing an identification of the processor in whose cache the data is held, and a d bit field for storing the true value of the G bit in rare situations. The memory controller comprises a data buffer, an address buffer, and a memory sequencer. The memory sequencer is a state machine for controlling the functions of the memory device.

Abstract: A system and method for multicasting control signals to selectively operate one memory device or groups of memory devices comprises a memory controller coupled to a plurality of memory devices by a command bus and a data bus. Each of the plurality of memory devices has a unique identification number. The system provides an addressing scheme in which an individual memory device or groups of memory device can be selected for operation by addressing the devices with a command packet. The memory controller broadcasts a command packet over the command bus to the plurality of memory devices. The packet includes an identification number. At each of the memory devices, selection logic is included to make the memory device operational if the identification number in the packet matches the identification number assigned to the memory device.

Abstract: A system for efficiently supporting critical-word-first data transfers comprises a data storage device, a controller, a data selector, and a multiplexer. The data storage device is preferably capable of outputting data in one or more word orderings. The controller is preferably a state machine that processes data transfer requests by determining the orderings of data that the associated data storage device, data selector and multiplexer can provide, determining the ordering for the data requested and creating a response packet with the data ordered in critical-word-aligned order beginning with the word containing the requested address. The present invention also includes a method for efficiently supporting critical-word-first data transfers.