Abstract: A double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) device incorporating a static random access memory (“SRAM”) cache per memory bank that provides effectively double peak data bandwidth, optimizes sustained bandwidth and improves bus efficiency as compared with conventional DDR SDRAM devices. The memory device disclosed provides effectively faster basic DRAM memory latency parameters, faster page “hit” latency, faster page “miss” latency and sustained bandwidth on random burst reads, faster read-to-write latency and write-to-read latency, hidden precharge, hidden bank activate latency, hidden refresh and hidden write precharge during a read “hit”.

Abstract: A cached synchronous dynamic random access memory (cached SDRAM) device having a multi-bank architecture and a programmable caching policy includes a synchronous dynamic random access memory (SDRAM) bank, a synchronous static randomly addressable row register, a select logic gating circuit, and mode register for programming of the cached SDRAM to operate in a Write Transfer mode corresponding to a Normal Operation mode of a standard SDRAM during a Write cycle, and to operate in a No Write Transfer mode according to an alternate operation mode during a Write cycle, thereby operating under a first and a second caching policy, respectively. The SDRAM includes a row decoder for selecting a row of data in a memory bank array, sense amplifiers for latching the row of data selected by the row decoder, and a synchronous column selector for selecting a desired column of the row of data.

Abstract: An apparatus for distributing the control of data transfers within single instruction stream multiple data stream processors. Each of the parallel processors or arithmetic units is coupled to a dedicated local memory. A main memory provides storage of system data. Each dedicated local memory and the main memory are coupled to a bus interface unit. Each bus interface unit is coupled to a common data bus for the transfer of data between the main memory and the dedicated local memories. Each bus interface unit provides the control functions required to transfer data between the common data bus and the main or local memory to which it is coupled. One bus interface unit is designated the resource controller. The resource controller performs all of the functions of a bus interface unit and also provides the system level functions of supplying clock signals and performing bus arbitration.

Abstract: An apparatus for automatically detecting overflow and imminent overflow conditions as data is transferred from an accumulator to a postscaler. As the data is output from the accumulator, the appropriateness of the predetermined scale factor to be used by the postscaler is determined. If an overflow condition will occur at the output of the postscaler, an overflow signal is generated, and the output of the postscaler is forced to .+-.1. If the output of the postscaler will produce data with an absolute value of greater than 1/2, an imminent overflow signal is generated.