Patents by Inventor David W. Burns

David W. Burns has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240150354
    Abstract: The present application provides tricyclic urea compounds that modulate the activity of the V617F variant of JAK2, which are useful in the treatment of various diseases, including cancer.
    Type: Application
    Filed: August 24, 2023
    Publication date: May 9, 2024
    Inventors: Yanran Ai, Onur Atasoylu, Yu Bai, Joseph Barbosa, David M. Burns, Daniel Levy, Brent Douty, Hao Feng, Leah C. Konkol, Cheng-Tsung Lai, Xun Liu, Song Mei, Jun Pan, Haisheng Wang, Liangxing Wu, Wenqing Yao, Eddy W. Yue
  • Patent number: 11925578
    Abstract: Certain aspects relate to drug delivery devices and methods for the treatment of ocular disorders requiring targeted and controlled administration of a drug to an interior portion of the eye. In several embodiments, the devices are capable of controlled release of two or more drugs, the release of each drug into a different ocular space (e.g., an ocular compartment versus an ocular fluid outflow pathway).
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: March 12, 2024
    Assignee: Glaukos Corporation
    Inventors: Harold A. Heitzmann, Thomas W. Burns, David S. Haffner
  • Patent number: 11926630
    Abstract: This application relates to compounds of Formula (I): or pharmaceutically acceptable salts thereof, which are inhibitors of PI3K-? which are useful for the treatment of disorders such as autoimmune diseases, cancer, cardiovascular diseases, and neurodegenerative diseases.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: March 12, 2024
    Assignee: Incyte Corporation
    Inventors: Brent Douty, Andrew W. Buesking, David M. Burns, Andrew P. Combs, Nikoo Falahatpisheh, Ravi Kumar Jalluri, Daniel Levy, Padmaja Polam, Lixin Shao, Stacey Shepard, Artem Shvartsbart, Richard B. Sparks, Eddy W. Yue
  • Publication number: 20240065887
    Abstract: Disclosed herein are drug delivery implants configured to be implanted into the eye of a subject and serve as intraocular drug depots. The implants reside in an intraocular target site until activation, at which time the implants release the drug (or drugs) housed within the implant in a controlled release fashion.
    Type: Application
    Filed: August 18, 2023
    Publication date: February 29, 2024
    Inventors: Harold A. Heitzmann, Thomas W. Burns, David S. Haffner
  • Publication number: 20210132793
    Abstract: A mobile display device may include a first display panel with a display screen having a viewing surface, a second display panel with a second display screen having a viewing surface, and a multi-position hinge coupling the first display panel to the second display panel. The first display panel and the second display panel may be configurable in a closed configuration, a paperback configuration, a tablet configuration, or a back-to-back configuration.
    Type: Application
    Filed: October 28, 2020
    Publication date: May 6, 2021
    Inventors: David W. Burns, Debra Brubaker Burns
  • Publication number: 20210124544
    Abstract: A mobile display device may include a first display panel with a display screen having a viewing surface and a second display panel with a display screen having a viewing surface. The display panels may be coupled with a multi-position hinge. A first operating system may be coupled to the first display panel and a second operating system may be coupled to the second display panel. The first operating system may operate independently of the second operating system and the second operating system may operate independently of the first operating system.
    Type: Application
    Filed: October 28, 2020
    Publication date: April 29, 2021
    Inventors: David W. Burns, Debra Brubaker Burns
  • Patent number: 10678712
    Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: June 9, 2020
    Assignee: Intel Corporation
    Inventors: Robert S. Chappell, John W. Faistl, Hermann W. Gartler, Michael D. Tucknott, Rajesh S. Parthasarathy, David W. Burns
  • Publication number: 20190188158
    Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.
    Type: Application
    Filed: February 11, 2019
    Publication date: June 20, 2019
    Inventors: Robert S. Chappell, John W. FAISTL, Hermann W. GARTLER, Michael D. TUCKNOTT, Rajesh S. PARTHASARATHY, David W. Burns
  • Patent number: 10216650
    Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: February 26, 2019
    Assignee: Intel Corporation
    Inventors: Robert S. Chappell, John W. Faistl, Hermann W. Gartler, Michael D. Tucknott, Rajesh S. Parthasarathy, David W. Burns
  • Publication number: 20180225228
    Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.
    Type: Application
    Filed: January 29, 2018
    Publication date: August 9, 2018
    Inventors: ROBERT S. CHAPPELL, JOHN W. FAISTL, HERMANN W. GARTLER, MICHAEL D. TUCKNOTT, RAJESH S. PARTHASARATHY, DAVID W. BURNS
  • Patent number: 9880948
    Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: January 30, 2018
    Assignee: INTEL CORPORATION
    Inventors: Robert S. Chappell, John W. Faistl, Hermann W. Gartler, Michael D. Tucknott, Rajesh S. Parthasarathy, David W. Burns
  • Patent number: 9626194
    Abstract: Method, apparatus, and system embodiments to assign priority to a thread when the thread is otherwise unable to proceed with instruction retirement. For at least one embodiment, the thread is one of a plurality of active threads in a multiprocessor system that includes memory livelock breaker logic and/or starvation avoidance logic. Other embodiments are also described and claimed.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: April 18, 2017
    Assignee: Intel Corporation
    Inventors: David W. Burns, K. S. Venkatraman
  • Publication number: 20170097902
    Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.
    Type: Application
    Filed: December 19, 2016
    Publication date: April 6, 2017
    Inventors: ROBERT S. CHAPPELL, JOHN W. FAISTL, HERMANN W. GARTLER, MICHAEL D. TUCKNOTT, RAJESH S. PARTHASARATHY, DAVID W. BURNS
  • Publication number: 20170023994
    Abstract: Method, apparatus, and system embodiments to assign priority to a thread when the thread is otherwise unable to proceed with instruction retirement. For at least one embodiment, the thread is one of a plurality of active threads in a multiprocessor system that includes memory livelock breaker logic and/or starvation avoidance logic. Other embodiments are also described and claimed.
    Type: Application
    Filed: September 24, 2012
    Publication date: January 26, 2017
    Inventors: David W. Burns, K. S. Venkatraman
  • Patent number: 9524263
    Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: December 20, 2016
    Assignee: Intel Corporation
    Inventors: Robert S. Chappell, John W. Faistl, Hermann W. Gartler, Michael D. Tucknott, Rajesh S. Parathasarthy, David W. Burns
  • Patent number: 8850165
    Abstract: In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: September 30, 2014
    Assignee: Intel Corporation
    Inventors: David W. Burns, James D. Allen, Michael D. Upton, Darrell D. Boggs, David J. Sager
  • Publication number: 20140267756
    Abstract: This disclosure provides systems, methods and apparatus for forming microbolometers on glass substrates. In one aspect, the formation of microbolometers on glass substrates can reduce the size and cost of the resultant array and associated circuitry. In one aspect, a portion of the measurement and control circuitry can be formed by thin-film deposition on the glass substrate, while sensitive measurement and control circuitry can be formed on ancillary CMOS substrates. In one aspect, the microbolometers may be packaged using a variety of techniques, including a wafer-level packaging process or a pixel-level packaging process.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: QUALCOMM MEMS Technologies, Inc.
    Inventors: Evgeni Gousev, David W. Burns, Nicholas I. Buchan, Ana R. Londergan
  • Publication number: 20140241785
    Abstract: A loose-leaf paper binder ring comprising a generally tubular shaped body; a first connecting end of said body arranged for releasably connecting with a complementary second connecting end for opening and closing the ring; a series of lower locking teeth being laterally spaced and extending along the length of said first connecting end; a series of upper locking teeth being laterally spaced and extending along the length of said second connecting end; whereby said upper locking teeth engage said lower locking teeth when said first connecting end is directly overlapped with said second connecting end; and, whereby a lateral displacement of said upper and lower locking teeth causes said first and second connecting ends to release.
    Type: Application
    Filed: February 27, 2013
    Publication date: August 28, 2014
    Inventor: David W. Burns
  • Publication number: 20140089931
    Abstract: Method, apparatus, and system embodiments to assign priority to a thread when the thread is otherwise unable to proceed with instruction retirement. For at least one embodiment, the thread is one of a plurality of active threads in a multiprocessor system that includes memory livelock breaker logic and/or starvation avoidance logic. Other embodiments are also described and claimed.
    Type: Application
    Filed: September 24, 2012
    Publication date: March 27, 2014
    Inventors: David W. Burns, K. S. Venkatraman
  • Publication number: 20140006661
    Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Inventors: Robert S. Chappell, John W. Faistl, Hermann W. Gartler, Michael D. Tucknott, Rajesh S. Parathasarthy, David W. Burns