Abstract: Clock signals are distributed on a chip by applying an oscillating magnetic field to the chip. Local clock generation circuits including magnetic field sensors are distributed around the chip and are coupled to local clocked circuitry on the chip. The magnetic field sensors may include clock magnetic tunnel junctions (MTJs) in which a magnetic orientation of the free layer is free to rotate in the free layer plane in response to the applied magnetic field. The MTJ resistance alternates between a high resistance value and a low resistance value as the free layer magnetization rotates. Clock generation circuitry coupled to the clock MTJs senses voltage oscillations caused by the alternating resistance of the clock MTJs. The clock generation circuitry includes amplifiers, which convert the sensed voltage into local clock signals.

Abstract: Clock signals are distributed on a chip by applying an oscillating magnetic field to the chip. Local clock generation circuits including magnetic field sensors are distributed around the chip and are coupled to local clocked circuitry on the chip. The magnetic field sensors may include clock magnetic tunnel junctions (MTJs) in which a magnetic orientation of the free layer is free to rotate in the free layer plane in response to the applied magnetic field. The MTJ resistance alternates between a high resistance value and a low resistance value as the free layer magnetization rotates. Clock generation circuitry coupled to the clock MTJs senses voltage oscillations caused by the alternating resistance of the clock MTJs. The clock generation circuitry includes amplifiers, which convert the sensed voltage into local clock signals.

Abstract: Embodiments disclosed herein address the need for a single wire bus interface. In one aspect, a device communicates with a second device via a single wire bus using a driver for driving the bus with a write frame comprising a start symbol, a write indicator symbol, an address, and data symbols. In another aspect, the device receives one or more data symbols on the single wire bus during a read frame. In yet another aspect, a device communicates with a second device via a single wire bus using a receiver for receiving a frame on the single wire bus comprising a start symbol, a write indicator symbol, an address, and one or more data symbols, and a driver for driving return read data associated with the address when the write indicator identifies a write frame. Various other aspects are also presented. These aspects provide for communication on a single wire bus, which allows for a reduction in pins, pads, or inter-block connections between devices.

Abstract: Adaptive voltage scalers (AVSs), systems, and related methods are disclosed. The AVSs are configured to adaptively adjust voltage levels powering a functional circuit(s) based on target operating frequencies and delay variation conditions to avoid or reduce voltage margin. In one embodiment, the AVS includes a database. The database can be configured to store voltage levels for various operating frequencies of a functional circuit(s) to avoid or reduce voltage margin. The database allows rapid voltage level decisions. In one embodiment, a voltage offset is added to a voltage level retrieved from the database corresponding to a target operating frequency of the functional circuit(s). In another embodiment, a voltage level is retrieved from the database corresponding to a target operating frequency for and a temperature level of the functional circuit(s). The AVS may partially or fully controllable by a software-based module that consults the database to make voltage level decisions.

Abstract: Adaptive voltage scalers (AVSs), systems, and related methods are disclosed. The AVSs are configured to adaptively adjust voltage levels powering a functional circuit(s) based on target operating frequencies and delay variation conditions to avoid or reduce voltage margin. In one embodiment, the AVS includes a database. The database can be configured to store voltage levels for various operating frequencies of a functional circuit(s) to avoid or reduce voltage margin. The database allows rapid voltage level decisions. In one embodiment, a voltage offset is added to a voltage level retrieved from the database corresponding to a target operating frequency of the functional circuit(s). In another embodiment, a voltage level is retrieved from the database corresponding to a target operating frequency for and a temperature level of the functional circuit(s). The AVS may partially or fully controllable by a software-based module that consults the database to make voltage level decisions.

Abstract: Built-in self-test (BIST) architecture having distributed interpretation and generalized command protocol is disclosed. In an embodiment, a system is disclosed and includes a centralized built-in self-test (BIST) controller configured to store an algorithm to test a plurality of memory modules. The BIST controller stores the algorithm as a set of generalized commands that conform to a command protocol. The BIST controller is configured to send the set of generalized commands to a sequencer.

Abstract: Embodiments disclosed herein address the need for a single wire bus interface. In one aspect, a device communicates with a second device via a single wire bus using a driver for driving the bus with a write frame comprising a start symbol, a write indicator symbol, an address, and data symbols. In another aspect, the device receives one or more data symbols on the single wire bus during a read frame. In yet another aspect, a device communicates with a second device via a single wire bus using a receiver for receiving a frame on the single wire bus comprising a start symbol, a write indicator symbol, an address, and one or more data symbols, and a driver for driving return read data associated with the address when the write indicator identifies a write frame. Various other aspects are also presented. These aspects provide for communication on a single wire bus, which allows for a reduction in pins, pads, or inter-block connections between devices.

Abstract: Built-in self-test (BIST) architecture having distributed interpretation and generalized command protocol is disclosed. In an embodiment, a system is disclosed and includes a centralized built-in self-test (BIST) controller configured to store an algorithm to test a plurality of memory modules. The BIST controller stores the algorithm as a set of generalized commands that conform to a command protocol. The BIST controller is configured to send the set of generalized commands to a sequencer.

Abstract: A built-in self-test (BIST) architecture having distributed algorithm interpretation is described. The architecture includes three tiers of abstraction: a centralized BIST controller, a set of sequencers, and a set of memory interfaces. The BIST controller stores a set of commands that generically define an algorithm for testing memory modules without regard to the physical characteristics or timing requirements of the memory modules. The sequencers interpret the commands in accordance with a command protocol and generate sequences of memory operations. The memory interfaces apply the memory operations to the memory module in accordance with physical characteristics of the memory module, e.g., by translating address and data signals based on the row-column arrangement of the memory modules to achieve bit patterns described by the commands. The command protocol allows powerful algorithms to be described in an extremely concise manner that may be applied to memory modules having diverse characteristics.

Abstract: A distributed, hierarchical built-in self-test (BIST) architecture for testing the operation of one or more memory modules is described. As described, the architecture includes three tiers of abstraction: a centralized BIST controller, a set of sequencers, and a set of memory interfaces coupled to memory modules. The BIST controller stores a set of commands that generically define an algorithm for testing the memory modules without regard to the physical characteristics or timing requirements of the memory modules. The sequencers receive the commands and generate sequences of memory operations in accordance with the timing requirements of the various memory modules. The memory interfaces apply the memory operations to the memory module in accordance with physical characteristics of the memory module, e.g., by translating address and data signals based on the row-column arrangement of the memory modules to achieve bit patterns described by the commands.

Abstract: A distributed, hierarchical built-in self-test (BIST) architecture for testing the operation of one or more memory modules is described. As described, the architecture includes three tiers of abstraction: a centralized BIST controller, a set of sequencers, and a set of memory interfaces coupled to memory modules. The BIST controller stores a set of commands that generically define an algorithm for testing the memory modules without regard to the physical characteristics or timing requirements of the memory modules. The sequencers receive the commands and generate sequences of memory operations in accordance with the timing requirements of the various memory modules. The memory interfaces apply the memory operations to the memory module in accordance with physical characteristics of the memory module, e.g., by translating address and data signals based on the row-column arrangement of the memory modules to achieve bit patterns described by the commands.

Abstract: The present invention discloses a method and apparatus for efficiently reading and storing state metrics in memory to enhance high-speed ACS Viterbi decoder implementations. The method includes applying an addressing scheme that determines the address locations of source state metrics during a process cycle. The source state metrics are then read from the address locations during the process cycle and applied to an add-compare-select butterfly operation of a Viterbi algorithm implementation to generate target state metrics. The method then stores each of the target state metrics into the address locations previously occupied by the source state metrics. The method further provides an addressing scheme that determines the address locations of the source state metrics based on a process cycle counter that is incremented and rotated in accordance with the process cycle.