Abstract: An apparatus includes a memory and a processor coupled to the memory. The processor is configured to perform the steps of: receiving a first head link for a page invalidation chain, the page invalidation chain including a plurality of page invalidation tables (PITs); receiving a second head link for an active real page table (RPT) chain, the active RPT chain including a plurality of RPTs; accessing a PIT, wherein the PIT includes a first data structure and a second data structure; invalidating the one or more RPTs, whereas the one or more RPTs are invalidated simultaneously in a batch; and releasing the one or more RPTs to a free RPT chain, the free RPT chain includes a plurality of released RPTs.

Abstract: An apparatus includes a memory and a processor coupled to the memory. The processor is configured to perform the steps of: receiving a first head link for a page invalidation chain, the page invalidation chain including a plurality of page invalidation tables (PITs); receiving a second head link for an active real page table (RPT) chain, the active RPT chain including a plurality of RPTs; accessing a PIT, wherein the PIT includes a first data structure and a second data structure; invalidating the one or more RPTs, whereas the one or more RPTs are invalidated simultaneously in a batch; and releasing the one or more RPTs to a free RPT chain, the free RPT chain includes a plurality of released RPTs.

Abstract: Systems and methods for network input/output affinity dispatching are provided. Embodiments may include detecting a completion of at least one of a network input operation and a network output operation, and identifying a communication task waiting for the completion. Embodiments may also include adjusting a first affinity queue associated with the communication task, and executing the communication task in accordance with the adjusted first affinity queue.

Abstract: The disclosure relates generally to managing assignment of tasks among instruction processors (IPs) within a computer system having multiple IPs, and more particularly to binding emulated IPs with a host system's IPs (e.g., processor cores) for facilitating control over affinity-based assignment of tasks among the host system's IPs by a task manager (e.g., OS) that is executing on the emulated IPs, rather than running directly on the host system's IPs. Certain embodiments provide techniques for binding emulated IPs with actual IPs of a computing system that is hosting the emulated IPs, thereby enabling better control of management of the system by a task manager executing on the emulated IPs. For instance, in certain embodiments, a dispatcher (e.g., of an OS running on emulated IPs) performs affinity-based management of task assignment for tasks performed for an application program among IPs of a host system that is hosting the emulated IPs.

Abstract: Systems and methods for testing and validation of translated memory banks used in an emulated system are disclosed. One method includes translating one or more banks of non-native instructions into one or more banks of native instructions executable in a computing system having a native instruction set architecture. The one or more banks of non-native instructions define one or more tests of execution of a non-native instruction set architecture. The method also includes loading a memory with instructions and data defined according to the non-native instruction set architecture and addressed by the one or more tests, and triggering, by an emulator, execution of the translated one or more banks of native instructions. The method further includes, upon detection of an error during execution of the translated one or more banks of native instructions, identifying an error in execution of the non-native instruction set architecture by the computing system.

Abstract: A computing system and method of executing a software program and translation of instructions for an emulated computing environment. The computing system includes a programmable circuit capable of executing native instructions of a first instruction set architecture and incapable of executing non-native instructions of a second instruction set architecture. The emulator operates within an interface layer and translates non-native applications hosted within an emulated operating system for execution. The computing system includes translated memory banks defined at least in part by the emulated operating system and capable of native execution on the programmable circuit, where the emulated operating system is incapable of execution on the programmable circuit.

Abstract: The disclosure relates generally to managing assignment of tasks among instruction processors (IPs) within a computer system having multiple IPs, and more particularly to binding emulated IPs with a host system's IPs (e.g., processor cores) for facilitating control over affinity-based assignment of tasks among the host system's IPs by a task manager (e.g., OS) that is executing on the emulated IPs, rather than running directly on the host system's IPs. Certain embodiments provide techniques for binding emulated IPs with actual IPs of a computing system that is hosting the emulated IPs, thereby enabling better control of management of the system by a task manager executing on the emulated IPs. For instance, in certain embodiments, a dispatcher (e.g., of an OS running on emulated IPs) performs affinity-based management of task assignment for tasks performed for an application program among IPs of a host system that is hosting the emulated IPs.

Abstract: A mechanism is disclosed for performing I/O operations using queue banks within a data processing system that supports multiple processing partitions. A queue bank is a re-useable area of memory allocated for performing I/O operations. All memory locking and address-translation functions are generally performed only once for a queue bank to reduce system overhead. After a queue bank has been used to perform an I/O operation, some processing is performed to make it available for re-use. This processing determines whether the queue bank contains memory that is being removed from a current processing partition. If so, a delay is imposed so that the queue bank is not made available for immediate re-use. This creates a window of time wherein all queue banks that contain the affected memory are inactive, thereby allowing the affected memory to be removed from the partition without halting on-going I/O activity.

Abstract: A mechanism is disclosed for performing I/O operations using queue banks within a data processing system that supports multiple processing partitions. A queue bank is a re-useable area of memory allocated for performing I/O operations. All memory locking and address-translation functions are generally performed only once for a queue bank to reduce system overhead. After a queue bank has been used to perform an I/O operation, some processing is performed to make it available for re-use. This processing determines whether the queue bank contains memory that is being removed from a current processing partition. If so, a delay is imposed so that the queue bank is not made available for immediate re-use. This creates a window of time wherein all queue banks that contain the affected memory are inactive, thereby allowing the affected memory to be removed from the partition without halting on-going I/O activity.

Abstract: Approaches for recovering state data between boot sessions of an emulated operating system (OS). An OS is emulated on a host OS. In response to each memory acquire request from the emulated OS, an interface to the host OS returns a memory area for use by the emulated OS and stores allocation data associated with the memory area. The allocation data includes an address referencing the memory area and a boot sequence number that indicates a boot session of the emulated OS. While booting the second emulated OS to a current boot session, the stored allocation data is retrieved from the interface, and in response to the stored allocation data including a selected boot sequence number, data from the memory area referenced by the address in the allocation data is stored in retentive storage by the second OS.

Abstract: A mechanism is disclosed for performing I/O operations using queue banks within a data processing system that supports multiple processing partitions. A queue bank is a re-useable area of memory allocated for performing I/O operations. All memory locking and address-translation functions are generally performed only once for a queue bank to reduce system overhead. After a queue bank has been used to perform an I/O operation, some processing is performed to make it available for re-use. This processing determines whether the queue bank contains memory that is being removed from a current processing partition. If so, a delay is imposed so that the queue bank is not made available for immediate re-use. This creates a window of time wherein all queue banks that contain the affected memory are inactive, thereby allowing the affected memory to be removed from the partition without halting on-going I/O activity.

Abstract: A mechanism is disclosed for performing I/O operations using queue banks within a data processing system that supports multiple processing partitions. A queue bank is a re-useable area of memory allocated for performing I/O operations. All memory locking and address-translation functions are generally performed only once for a queue bank to reduce system overhead. After a queue bank has been used to perform an I/O operation, some processing is performed to make it available for re-use. This processing determines whether the queue bank contains memory that is being removed from a current processing partition. If so, a delay is imposed so that the queue bank is not made available for immediate re-use. This creates a window of time wherein all queue banks that contain the affected memory are inactive, thereby allowing the affected memory to be removed from the partition without halting on-going I/O activity.

Abstract: Disclosure of approaches for stabilizing an emulated system. In one approach, a first operating system (OS) is executed on an instruction processor, the first OS including instructions native to the instruction processor. A second OS and a plurality of application programs are emulated on the first OS. The second OS polls the first OS for memory statistics of the first OS. The memory statistics indicate a current state of operating parameters of the memory of the data processing system used by the first OS in managing the data processing system. The second OS controls a number of the application programs allowed to execute in response to the memory statistics provided by the first OS to the second OS.

Abstract: A memory management interface is provided to synchronize the operation of two disparate operating systems (OSes) that are executing on the same data processing platform. In one embodiment, the first operating system is a legacy OS of the type that is generally associated with an enterprise-level data processing system such as a mainframe. In contrast, the second OS is of a type designed to execute on commodity hardware such as personal computers. The first OS communicates with the second OS via a control logic interface to establish its execution environment, and to perform memory management functions. This interface supports a two-phase boot process that ensures that all memory allocated to the first OS can be released if an error occurs that affects operations of the first OS. This prevents the development of memory leaks.