Abstract: In one embodiment, a lidar system includes a light source configured to emit local-oscillator (LO) light and pulses of light, the emitted pulses of light including a first emitted pulse of light, where an optical frequency of the first emitted pulse of light is offset from an optical frequency of the LO light by a first frequency offset. The lidar system further includes a receiver configured to detect the LO light and a first received pulse of light, the first received pulse of light including light from the first emitted pulse of light scattered by a target located a distance from the lidar system. The receiver includes a detector, where: the LO light and the first received pulse of light are coherently mixed together at the detector, and the detector is configured to produce a photocurrent signal corresponding to the coherent mixing.

Abstract: A memory including an array of nvRAM cells and method of operating the same, where each nvRAM cell includes a volatile charge storage circuit, and a nonvolatile charge storage circuit including a solitary non-volatile memory (NVM) device, a first transistor coupled to the NVM device through which data is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM device through which a compliment of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM device is coupled to a positive voltage supply line (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM device, the second transistor is coupled to a second node of the NVM device and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed.

Abstract: A memory including an array of nvRAM cells and method of operating the same are provided. Each nvRAM cell includes a volatile charge storage circuit, and a non-volatile charge storage circuit including a solitary non-volatile memory (NVM) device, a first transistor coupled to the NVM device through which data is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM device through which a compliment of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM device is coupled to a positive voltage supply line (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM device, the second transistor is coupled to a second node of the NVM device and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed.

Abstract: A memory cell includes a storage element coupled to a first data node and a second data node, a first programmable nonvolatile element and a second programmable nonvolatile element, a first switch element and a second switch element. The first switch element is configured to couple the first programmable nonvolatile element to the first data node during a first read mode of the memory cell. The second switch element is configured to couple the second programmable nonvolatile element to the second data node during the first read mode.

Abstract: A semiconductor memory array having a first memory cell array with a number of first memory cells and a second cell array with a number of second memory cells. The memory cells in the first and second memory cell arrays are arranged in rows and columns. Each column of second memory cells in the second memory array is coupled to a column of first memory cells in the first memory array.

Abstract: A system and method for programming and erasing a semiconductor memory is disclosed. More particularly, the present invention uses the bit lines of a volatile memory portion of semiconductor memory so as to program and erase the non-volatile portion of the semiconductor memory.

Abstract: A system and method for programming both sides of the non-volatile portion in a semiconductor memory is disclosed. The present invention erases and then programs the memory stacks in the non-volatile portion of an nvSRAM.

Abstract: A system and method for disturbing an erased memory location structure in a non-volatile portion of a semiconductor memory is disclosed. The present invention applies a voltage to a first memory location of a non-volatile portion of the semiconductor memory that is in a programmed state and a second memory location of a non-volatile portion of the semiconductor memory that is in an erased state so as to keep the first memory location programmed and to transition the second memory location from a programmed state to an erased state.

Abstract: A system and method for programming and erasing a semiconductor memory is disclosed. More particularly, the present invention uses the bit lines of a volatile memory portion of semiconductor memory so as to program and erase the non-volatile portion of the semiconductor memory.

Abstract: A semiconductor memory array having a first memory cell array with a number of first memory cells and a second cell array with a number of second memory cells. The memory cells in the first and second memory cell arrays are arranged in rows and columns. Each column of second memory cells in the second memory array is coupled to a column of first memory cells in the first memory array.

Abstract: A system and method for programming both sides of the non-volatile portion in a semiconductor memory is disclosed. The present invention erases and then programs the memory stacks in the non-volatile portion of an nvSRAM.

Abstract: A system and method for disturbing an erased memory location structure in a non-volatile portion of a semiconductor memory is disclosed. The present invention applies a voltage to a first memory location of a non-volatile portion of the semiconductor memory that is in a programmed state and a second memory location of a non-volatile portion of the semiconductor memory that is in an erased state so as to keep the first memory location programmed and to transition the second memory location from a programmed state to an erased state.

Abstract: The present invention is a combined pencil sharpener and pencil stowage apparatus. The invention comprises a body, a pencil stowage compartment formed within the body for containing a tip of a pencil, and a separate pencil sharpener compartment formed within the body, the pencil sharpener compartment containing a pencil sharpener. Unlike previous inventions, the present invention provides a single body that has these two separate pencil stowage and pencil sharpener compartments formed therein. The pencil stowage compartment and pencil sharpener compartment are preferably positioned in a parallel relationship to minimize the length of the pencil/apparatus when the pencil is stowed in the apparatus, therefore making it easy to be stored in the user's pocket.

Abstract: A programmable circuit array comprises an input buffer adapted to receive a plurality of input signals for outputting equivalent input signals and inverted input signals. A programmable product array receives the equivalent input signals and the inverted input signals, for generating a plurality of logical product terms. A programmable sum array combines the plurality of product terms to generate a plurality of sum terms, each of the plurality of sum terms being an output of the programmable circuit array. Test logic is included which selectively causes each of the product terms, the equivalent input signals, and the inverted input signals to have a predetermined logic state in response to at least one control signal.

Abstract: The present invention relates to a dynamically testable programmable logic array in an unprogrammed state which adds some circuit components to the static test logic. The static test logic provides the capability to detect stuck-at faults at the input of each logic gate of the programmable logic array, and is inoperative during normal operation of the programmable logic array. The added circuit components cause selected inputs to the product array to partially enable the product array, whereby the remaining inputs to the product array are a function of the inputs to the programmable logic array, thereby providing the dynamic test capability.