Patents by Inventor David Warren Pruden

David Warren Pruden has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Implementing logic security feature for disabling integrated circuit test ports ability to scanout data
    Patent number: 8166357
    Abstract: A method and apparatus for implementing integrated circuit security features are provided to selectively disable testability features on an integrated circuit chip. A test disable logic circuit receives a test enable signal and responsive to the test enable signal set for a test mode, establishes a test mode and disables ASIC signals. Responsive to the test enable signal not being set, the ASIC signals are enabled for a functional mode and the testability features on the integrated circuit chip are disabled. When the functional mode is enabled, the test disable logic circuit prevents the test mode from being established while the integrated circuit chip is powered up.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: April 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: David Warren Pruden, Dennis Martin Rickert, Brian Andrew Schuelke
  • Method and Apparatus for Implementing Logic Security Feature for Disabling Integrated Circuit Test Ports Ability to Scanout Data
    Publication number: 20090172819
    Abstract: A method and apparatus for implementing integrated circuit security features are provided to selectively disable testability features on an integrated circuit chip. A test disable logic circuit receives a test enable signal and responsive to the test enable signal set for a test mode, establishes a test mode and disables ASIC signals. Responsive to the test enable signal not being set, the ASIC signals are enabled for a functional mode and the testability features on the integrated circuit chip are disabled. When the functional mode is enabled, the test disable logic circuit prevents the test mode from being established while the integrated circuit chip is powered up.
    Type: Application
    Filed: December 26, 2007
    Publication date: July 2, 2009
    Inventors: David Warren Pruden, Dennis Martin Rickert, Brian Andrew Schuelke