Abstract: A method and system for speculatively issuing instructions which are dependent upon results from execution of other instructions. Instructions are speculatively issued, dependent upon a result from execution of a primary instruction, wherein the speculatively issued instructions are issued after execution of the primary instruction. N clock cycles are tracked after execution of the primary instruction, wherein the result from execution of said primary instruction is expected within n clock cycles. Execution of any speculatively issued instructions which are dependent upon the primary instruction is cancelled if the result is not returned from execution of the primary instruction within n clock cycles, such that for primary instructions for which the result is returned within the expected n clock cycles any speculatively issued instructions dependent upon said result are executed with increased efficiency.

Abstract: An information handling system which efficiently processes auxiliary functions such as graphics processing includes one or more processors, a high speed processor bus connecting the one or more processors, a memory controller for controlling memory and for controlling the auxiliary function processing, a memory system, and an I/O bus having one or more I/O controllers with I/O devices connected thereto.

Abstract: To present a consistent image of storage facilities to components in Bi-modal Endian PowerPC system enviromnents, provision is made for transferring data between system components in the appropriate Endian format. Endian conversion function can be incorporated into the memory controller subsystem by adding byte-lane swapping logic on the inbound and outbound I/O data paths. With this structure, inbound data from the processor and memory bus will be converted to true Little Endian order before being sent to I/O devices. Likewise, true Little Endian data from I/O devices targeted for the processor or memory is modified to reflect the PowerPC Little Endian byte ordering convention.

Abstract: PowerPC external control instructions are utilized to pass a translated address to a transfer engine located in the system memory controller, together with previously transferred parameters into control registers within the memory controller. An accelerated data movement is accomplished between system memory and an input/output device with a minimum of processor overhead and bus bandwidth utilization. This method is useful for transferring large amounts of data between memory and such devices as graphics adapters or multimedia devices.