Abstract: Sequential fetch requests from a set of fetch requests are combined into longer coalesced requests that match the width of a system memory interface in order to improve memory access efficiency for reading the data specified by the fetch requests. The fetch requests may be of different classes and each data class is coalesced separately, even when intervening fetch requests are of a different class. Data read from memory is ordered according to the order of the set of fetch requests to produce an instruction stream that includes the fetch requests for the different classes.

Abstract: A system and method dispatches commands from multiple instruction streams to processing engines, allowing for some of the dispatched commands to be rescinded before they are executed by the processing engines. The dispatching enables several of the processing engines to execute commands concurrently. Dispatched commands may be rescinded to quickly switch processing from one instruction stream to another instruction stream.

Abstract: Sequential fetch requests from a set of fetch requests are combined into longer coalesced requests that match the width of a system memory interface in order to improve memory access efficiency for reading the data specified by the fetch requests. The fetch requests may be of different classes and each data class is coalesced separately, even when intervening fetch requests are of a different class. Data read from memory is ordered according to the order of the set of fetch requests to produce an instruction stream that includes the fetch requests for the different classes.

Abstract: Sequential fetch requests from a set of fetch requests are combined into longer coalesced requests that match the width of a system memory interface in order to improve memory access efficiency for reading the data specified by the fetch requests. The fetch requests may be of different classes and each data class is coalesced separately, even when intervening fetch requests are of a different class. Data read from memory is ordered according to the order of the set of fetch requests to produce an instruction stream that includes the fetch requests for the different classes.

Abstract: A data processing system can establish or maintain data coherency by issuing a data flush operation. The data processing system can be configured as a host executing one or more independent processes using one or more lower level devices. The lower level devices can be viewed as peer devices. Any of the host or the plurality of peer devices can be configured to initiate the flush operation. A device can determine whether the initiator of a flush operation is the host or a peer device. The device can perform a flush limited to local memory, or a subset of all available memory, if a peer device initiates the flush operation.

Abstract: The display buffer of a multimedia workstation is partitioned into a display section and a non-display section. The information to be displayed on the display screen is arranged in the display section of the display buffer. An image or shadow of the display section is written in the non-display section (called a lock buffer) of the display buffer. Prior to updating the display section, a controller reads the protection data from the lock buffer and generates control signals which inhibit the writing of data into protected areas of the display section.

Abstract: The display buffer of a multimedia workstation is partitioned into a display section and a non-display section. The information to be displayed on the display screen is arranged in the display section of the display buffer. An image or shadow of the display section is written in the non-display section (called a lock buffer) of the display buffer. Prior to updating the display section, a controller reads the protection data from the lock buffer and generates control signals which inhibit the writing of data into protected areas of the display section.

Abstract: A programmable memory controller includes a plurality of multi-bit registers, with each multi-bit register coupled to a cycle generator. Each cycle generator is formed from a multi-bit shift register and control signals which drive each multi-bit shift register so that data in an associated multi-bit register is shifted through the shift register to form desired memory control pulses.