Patents by Inventor Davide Mantegazza
Davide Mantegazza has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240092723Abstract: The present invention concerns a method to prepare and purify the ester glyceryl-tris-(3-hydroxy butyrate) of formula (I) and its optically active isomers, in particular the enantiomer (R, R, R).Type: ApplicationFiled: October 6, 2020Publication date: March 21, 2024Applicant: DR. SCHAR S.P.A.Inventors: Virna Lucia Cerne, Gabriele Razzetti, Simone Mantegazza, Roberto Rossi, Philippe Carboni, Niccolo Santillo, Davide Brenna, Emanuele Attolino
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Patent number: 11626161Abstract: A selection scheme for crosspoint memory is described. In one example, the selection voltage applied across the memory cell is slowly ramped up. Once the memory cell thresholds, the voltage is reduced to a level for performing the read or write operation. Reducing the voltage once the specific cell has been selected (e.g., thresholds) minimizes the additional transient current which might be generated by further increasing the selection bias applied during read or write operation. The reduction in transient current can lead to an improvement in read disturb and write endurance issues. The selection ramp-rate and bias post-selection can be set differently depending on the cell location inside the memory array to further improve cell performance.Type: GrantFiled: July 6, 2021Date of Patent: April 11, 2023Assignee: Intel CorporationInventors: Davide Mantegazza, Kyung Jean Yoon, John Gorman, Dany-Sebastien Ly-Gagnon
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Publication number: 20220254999Abstract: A memory cell design is disclosed. The design is particularly well-suited for three-dimensional cross-point (3D X-point) memory configurations. Various embodiments of the memory cell design include one or more electrodes having an increased resistance compared to existing memory cell designs or compared to other electrodes within a same memory cell. A memory device includes an array of memory cells with each memory cell arranged between a word line and a bit line of the memory device. Some embodiments include additional material layers to increase memory cell resistance. Some embodiments include electrodes having an increased thickness to increase the resistance. Some embodiments include electrodes having a composition with a higher resistivity. Some embodiments include electrodes with increased interface resistance. Some embodiments include a combination of such features.Type: ApplicationFiled: February 28, 2022Publication date: August 11, 2022Inventors: Srivatsan VENKATESAN, Davide MANTEGAZZA, John GORMAN, Iniyan Soundappa ELANGO, Davide FUGAZZA, Andrea REDAELLI, Fabio PELLIZZER
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Patent number: 11264567Abstract: Various embodiments of a three-dimensional cross-point (3D X-point) memory cell design include one or more electrodes having an increased resistance compared to existing memory cell designs or compared to other electrodes within a same memory cell. A memory device includes an array of memory cells with each memory cell arranged between a word line and a bit line of the memory device. Some embodiments include additional material layers to increase memory cell resistance. Some embodiments include electrodes having an increased thickness to increase the resistance. Some embodiments include electrodes having a composition with a higher resistivity. Some embodiments include electrodes with increased interface resistance. Some embodiments include a combination of such features. In any case, the resulting increased memory cell resistance causes a reduction in the transient selection current for the given memory cell.Type: GrantFiled: November 19, 2019Date of Patent: March 1, 2022Assignee: Intel CorporationInventors: Srivatsan Venkatesan, Davide Mantegazza, John Gorman, Iniyan Soundappa Elango, Davide Fugazza, Andrea Redaelli, Fabio Pellizzer
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Publication number: 20210335419Abstract: A selection scheme for crosspoint memory is described. In one example, the selection voltage applied across the memory cell is slowly ramped up. Once the memory cell thresholds, the voltage is reduced to a level for performing the read or write operation. Reducing the voltage once the specific cell has been selected (e.g., thresholds) minimizes the additional transient current which might be generated by further increasing the selection bias applied during read or write operation. The reduction in transient current can lead to an improvement in read disturb and write endurance issues. The selection ramp-rate and bias post-selection can be set differently depending on the cell location inside the memory array to further improve cell performance.Type: ApplicationFiled: July 6, 2021Publication date: October 28, 2021Inventors: Davide MANTEGAZZA, Kyung Jean YOON, John GORMAN, Dany-Sebastien LY-GAGNON
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Patent number: 11145366Abstract: Examples may include techniques to mitigate errors during a read operation to a memory cell of a memory array. Examples include selecting the memory cell and applying one of multiple demarcation read voltages for respective multiple time intervals to sense a state of a resistive storage element of the memory cell. Examples also include applying a bias voltage to the memory cell following a sense interval to mitigate read disturb to the resistive storage element incurred while the one of the multiple demarcation read voltages was applied to the memory cell.Type: GrantFiled: March 24, 2020Date of Patent: October 12, 2021Assignee: Intel CorporationInventors: Davide Mantegazza, Kiran Pangal
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Publication number: 20210304817Abstract: Examples may include techniques to mitigate errors during a read operation to a memory cell of a memory array. Examples include selecting the memory cell and applying one of multiple demarcation read voltages for respective multiple time intervals to sense a state of a resistive storage element of the memory cell. Examples also include applying a bias voltage to the memory cell following a sense interval to mitigate read disturb to the resistive storage element incurred while the one of the multiple demarcation read voltages was applied to the memory cell.Type: ApplicationFiled: March 24, 2020Publication date: September 30, 2021Inventors: Davide MANTEGAZZA, Kiran PANGAL
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Patent number: 11100987Abstract: A selection scheme for crosspoint memory is described. In one example, the selection voltage applied across the memory cell is slowly ramped up. Once the memory cell thresholds, the voltage is reduced to a level for performing the read or write operation. Reducing the voltage once the specific cell has been selected (e.g., thresholds) minimizes the additional transient current which might be generated by further increasing the selection bias applied during read or write operation. The reduction in transient current can lead to an improvement in read disturb and write endurance issues. The selection ramp-rate and bias post-selection can be set differently depending on the cell location inside the memory array to further improve cell performance.Type: GrantFiled: March 26, 2020Date of Patent: August 24, 2021Assignee: Intel CorporationInventors: Davide Mantegazza, Kyung Jean Yoon, John Gorman, Dany-Sebastien Ly-Gagnon
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Patent number: 11087854Abstract: A high current fast read scheme can enable improved read disturb without negatively impacting read performance. In one example, a fast read scheme involves applying a higher current as soon as the cell thresholds. In one example, circuitry detects the threshold event and turns on a bypass control transistor to bypass the circuitry applying the read voltage to enable a higher voltage and therefore higher current as soon as possible. The read time can thus be decreased (or at least not increased) and read disturb improved.Type: GrantFiled: March 5, 2020Date of Patent: August 10, 2021Assignee: Intel CorporationInventor: Davide Mantegazza
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Patent number: 11081151Abstract: Examples may include techniques to improve a read operation to a memory array. Examples include identifying characteristics of memory cells in the memory array such as relative positions of memory cells within the memory array and then set multiple read reference voltages or currents to detect a memory state of memory cells based on identified characteristics.Type: GrantFiled: September 26, 2019Date of Patent: August 3, 2021Assignee: Intel CorporationInventor: Davide Mantegazza
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Publication number: 20210151672Abstract: A memory cell design is disclosed. The design is particularly well-suited for three-dimensional cross-point (3D X-point) memory configurations. Various embodiments of the memory cell design include one or more electrodes having an increased resistance compared to existing memory cell designs or compared to other electrodes within a same memory cell. A memory device includes an array of memory cells with each memory cell arranged between a word line and a bit line of the memory device. Some embodiments include additional material layers to increase memory cell resistance. Some embodiments include electrodes having an increased thickness to increase the resistance. Some embodiments include electrodes having a composition with a higher resistivity. Some embodiments include electrodes with increased interface resistance. Some embodiments include a combination of such features.Type: ApplicationFiled: November 19, 2019Publication date: May 20, 2021Applicant: INTEL CORPORATIONInventors: SRIVATSAN VENKATESAN, DAVIDE MANTEGAZZA, JOHN GORMAN, INIYAN SOUNDAPPA ELANGO, DAVIDE FUGAZZA, ANDREA REDAELLI, FABIO PELLIZZER
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Publication number: 20210098034Abstract: Examples may include techniques to improve a read operation to a memory array. Examples include identifying characteristics of memory cells in the memory array such as relative positions of memory cells within the memory array and then set multiple read reference voltages or currents to detect a memory state of memory cells based on identified characteristics.Type: ApplicationFiled: September 26, 2019Publication date: April 1, 2021Inventor: Davide MANTEGAZZA
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Patent number: 10957387Abstract: Techniques for accessing multi-level cell (MLC) crosspoint memory cells are described. In one example, a circuit includes a crosspoint memory cell that can be in one of multiple resistive states (e.g., four or more resistive states). In one example, to perform a read, circuitry coupled with the memory cell applies one or more sub-reads at different read voltages. For example, the circuitry applies a first read voltage and detects if the memory cell thresholds in response to the first read voltage. If the memory cell thresholded in response to the first read voltage, the state of the memory cell can be determined without further reads. If the memory cell did not threshold in response to the first read voltage, a second read voltage with a greater magnitude is applied across the memory cell. If the memory cell thresholded in response to the second read voltage, the state of the memory cell can be determined without further reads.Type: GrantFiled: November 18, 2019Date of Patent: March 23, 2021Assignee: Intel CorporationInventors: Davide Mantegazza, Kiran Pangal, Sanjay Rangan
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Patent number: 10902911Abstract: Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and methods, are provided and discussed.Type: GrantFiled: November 6, 2019Date of Patent: January 26, 2021Assignee: Intel CorporationInventors: Davide Mantegazza, Sandeep Guliani, Balaji Srinivasan, Kiran Pangal
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Publication number: 20200159424Abstract: Deck offset techniques for multi-deck non-volatile memory can reduce the average raw bit error rate (RBER) for a memory system. Deck offset can enable accessing different physical decks for the same input deck address. In one example in a system with multiple memory components, different physical decks are accessed across multiple memory components for the same logical deck address. In one example in a system with one memory component, different physical decks are accessed across multiple partitions of the same memory component.Type: ApplicationFiled: January 24, 2020Publication date: May 21, 2020Inventors: Ashir G. SHAH, Prashant DAMLE, Davide MANTEGAZZA
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Publication number: 20200143881Abstract: Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and methods, are provided and discussed.Type: ApplicationFiled: November 6, 2019Publication date: May 7, 2020Applicant: Intel CorporationInventors: Davide Mantegazza, Sandeep Guliani, Balaji Srinivasan, Kiran Pangal
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Patent number: 10475508Abstract: Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and methods, are provided and discussed.Type: GrantFiled: December 26, 2017Date of Patent: November 12, 2019Assignee: Intel CorporationInventors: Davide Mantegazza, Sandeep Guliani, Balaji Srinivasan, Kiran Pangal
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Patent number: 10431270Abstract: Apparatuses for increasing the voltage budget window of a memory array are described. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. The threshold voltage of the selected cell may decrease responsive to the pre-bias voltage. Conversely, threshold voltage of deselected cells coupled to only one of the memory access lines coupled to the selected cell may increase responsive to the pre-bias voltage. The decrease of the threshold voltage of the selected cell and the increase of the threshold voltage of the deselected cells may increase the voltage window of the memory array.Type: GrantFiled: December 29, 2017Date of Patent: October 1, 2019Assignee: Micron Technology, Inc.Inventors: Davide Mantegazza, Kiran Pangal, Feng Q. Pan, Hernan A. Castro, DerChang Kau
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Publication number: 20180286478Abstract: Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and methods, are provided and discussed.Type: ApplicationFiled: December 26, 2017Publication date: October 4, 2018Applicant: Intel CorporationInventors: Davide Mantegazza, Sandeep Guliani, Balaji Srinivasan, Kiran Pangal
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Publication number: 20180151206Abstract: Apparatuses for increasing the voltage budget window of a memory array are described. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. The threshold voltage of the selected cell may decrease responsive to the pre-bias voltage. Conversely, threshold voltage of deselected cells coupled to only one of the memory access lines coupled to the selected cell may increase responsive to the pre-bias voltage. The decrease of the threshold voltage of the selected cell and the increase of the threshold voltage of the deselected cells may increase the voltage window of the memory array.Type: ApplicationFiled: December 29, 2017Publication date: May 31, 2018Applicant: Micron Technology, Inc.Inventors: Davide Mantegazza, Kiran Pangal, Feng Q. Pan, Hernan A. Castro, DerChang Kau