Abstract: The present disclosure addresses a concept for capacitor scaling. A first capacitor is provided with a first signal capacitance between a first electrode and a second electrode of the first capacitor and with a first parasitic capacitance between the first capacitor's first electrode and AC ground. A sum of the first signal capacitance and the first parasitic capacitance yields a first total capacitance. A second capacitor is provided with a second signal capacitance between a first electrode and a second electrode of the second capacitor and with a second parasitic capacitance between the second capacitor's first electrode and AC ground. A sum of the second signal capacitance and the second parasitic capacitance yields a second total capacitance. While the first signal capacitance differs from the second signal capacitance, the first total capacitance equals the second total capacitance.

Abstract: The present disclosure addresses a concept for capacitor scaling. A first capacitor is provided with a first signal capacitance between a first electrode and a second electrode of the first capacitor and with a first parasitic capacitance between the first capacitor's first electrode and AC ground. A sum of the first signal capacitance and the first parasitic capacitance yields a first total capacitance. A second capacitor is provided with a second signal capacitance between a first electrode and a second electrode of the second capacitor and with a second parasitic capacitance between the second capacitor's first electrode and AC ground. A sum of the second signal capacitance and the second parasitic capacitance yields a second total capacitance. While the first signal capacitance differs from the second signal capacitance, the first total capacitance equals the second total capacitance.

Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a plurality of digital-to-analog converter cells coupled to an output node of the digital-to-analog converter. At least one of the plurality of digital-to-analog converter cells includes a capacitive element configured to generate an analog cell output signal based on a drive signal. The at least one of the plurality of digital-to-analog converter cells further includes a driver circuit configured to generate the drive signal, and a resistive element exhibiting a resistance of at least 20?. The resistive element is coupled between the driver circuit and the capacitive element or between the capacitive element and the output node.

Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a plurality of digital-to-analog converter cells coupled to an output node of the digital-to-analog converter. At least one of the plurality of digital-to-analog converter cells includes a capacitive element configured to generate an analog cell output signal based on a drive signal. The at least one of the plurality of digital-to-analog converter cells further includes a driver circuit configured to generate the drive signal, and a resistive element exhibiting a resistance of at least 20?. The resistive element is coupled between the driver circuit and the capacitive element or between the capacitive element and the output node.

Abstract: A radio frequency digital-to-analog converter (RFDAC) circuit includes an RFDAC array circuit including an array of cells arranged into a plurality of segments. Each segment of the plurality of segments is configured to process input data signals. The RFDAC array circuit is configured to process an input data based on activating a set of segments of the plurality of segments, forming a set of active segments, and when the sign of the input data is changed, deactivate a partially active segment of the set of active segments and activate a sign change segment within the RFDAC array circuit. The sign change segment includes a segment within the plurality of segments of the RFDAC array circuit that is different from the set of active segments.

Abstract: Apparatus and methods for a digital-to-time converter (DTC) are provided. In an example, a DTC can include a phase interpolator and a ring oscillator. The phase interpolator can be configured to receive digital representations of two or more distinct phase signals, and to interpolate the digital representations of the two or more distinct phase signals to provide an interpolated output phase signal. The ring oscillator can be configured to receive the interpolated phase signal, to lock on to a frequency and a phase of the interpolated output phase signal, and to provide a filtered phase signal.

Abstract: A digital to analog converter circuit includes a plurality of digital to analog converter cells. The digital to analog converter circuit further includes a control circuit configured to control an operation of a digital to analog converter cell of the plurality of digital to analog converter cells based on a first phase component of a digital signal comprising information to be transmitted during a first time interval and based on a second phase component of the digital signal comprising information to be transmitted during a second time interval.

Abstract: Apparatus and methods for a digital-to-time converter (DTC) are provided. In an example, a DTC can include a phase interpolator and a ring oscillator. The phase interpolator can be configured to receive digital representations of two or more distinct phase signals, and to interpolate the digital representations of the two or more distinct phase signals to provide an interpolated output phase signal. The ring oscillator can be configured to receive the interpolated phase signal, to lock on to a frequency and a phase of the interpolated output phase signal, and to provide a filtered phase signal.

Abstract: A digital to analog converter circuit includes a plurality of digital to analog converter cells. The digital to analog converter circuit further includes a control circuit configured to control an operation of a digital to analog converter cell of the plurality of digital to analog converter cells based on a first phase component of a digital signal comprising information to be transmitted during a first time interval and based on a second phase component of the digital signal comprising information to be transmitted during a second time interval.

Abstract: Devices are provided comprising oscillator circuits coupled to a supply voltage via an adjustable resistance. Corresponding methods to control adjustable resistances are also provided.

Abstract: A phase interpolator is provided. The phase interpolator includes a plurality of capacitors, a first input for a clock signal, a second input for a phase shifted clock signal, a reference input for a reference signal, and an output. The phase interpolator is configured to provide at its output an interpolated, modulated phase information signal by switching, dependent on a modulation information, a first number of the capacitors between the first input and the output, a second number of the capacitors between the second input and the output, and a third number of the capacitors to the reference input.

Abstract: A phase interpolator is provided. The phase interpolator includes a plurality of capacitors, a first input for a clock signal, a second input for a phase shifted clock signal, a reference input for a reference signal, and an output. The phase interpolator is configured to provide at its output an interpolated, modulated phase information signal by switching, dependent on a modulation information, a first number of the capacitors between the first input and the output, a second number of the capacitors between the second input and the output, and a third number of the capacitors to the reference input.

Abstract: Devices are provided comprising oscillator circuits coupled to a supply voltage via an adjustable resistance. Corresponding methods to control adjustable resistances are also provided.