Abstract: The Logic Analyzer Probe Board is a hardware design which allows convenient access to signals on a printed circuit board. On one side of the Probe Board assembly is a collection of probes that provide contact to the printed-circuit boards pads, pins, vias and test points on the non-component side of a UUT. The other side of the Probe Board assembly contains an organized collection of connectors, or headers, that connect to a logic analyzer's cable harness. When the Probe Board mates with the printed circuit board, the Probe Board taps into a printed circuit board's signal via the probe-to-pad connection and routes the detected signal via one of the header pins to the logic analyzer. The design of the printed circuit board includes test points that correspond to each signal under test. Once the layout of a printed circuit board is determined, a custom-designed Probe Board may be designed that is cable of accessing each test point.

Abstract: The gangSIMM Memory Tester is a PWA which plugs directly into a CPU's SIMM slot. The gangSIMM Memory Tester contains a known good SIMM, which is connected directly to the CPU's bus. All memory functions for this SIMM slot is provided by the gold SIMM per normal SIMM operation. The CPU bus routed to the gold SIMM on the gangSIMM Memory Tester is also routed to a test bus via a buffer which provides increased drive capacity. The test bus is distributed in parallel to N number of SIMM slots located on the gangSIMM Memory Tester throughout a second set of tri-stating buffers. During read accesses to memory involving the CPUs SIMM slot location where the gangSIMM PWA is directly plugged into, data provided by the gold SIMM is compared on an individual basis with the data provided by an under-test SIMM. This operation occurs in-parallel for all under-test SIMMs.

Abstract: An application specific integrated circuit (ASIC) includes ASIC logic, test logic, dual function input test cells and dual function output test cells. The test logic with the input and output test cells provides manufacturing test capability for the ASIC logic with a plurality of input pins and a plurality of output pins while reducing both the gate count and signal time delay associated with the input and output test cells. Each input test cell includes a boundary scan circuit means and a built-in self-test circuit means. An input test cell has a signal propagation time delay for a signal, that travels from an input pin to an ASIC logic input line, equivalent to one two-to-one multiplexer signal propagation delay. Hence, while the input test cell has the capability of both built-in self-test and boundary scan testing, the dual capability is achieved without incurring a signal propagation time delay for each capability.

Abstract: An application specific integrated circuit (ASIC) includes ASIC logic and test logic that includes a fail-safe circuit and test logic circuitry. The test logic in conjunction with input and output test cells provides manufacturing test capability for the ASIC logic with a plurality of input pins and a plurality of output pins. The test logic generates several control signals that can affect operation of the ASIC logic. If any one of these signals is driven active by either a failure or a defect, the ASIC logic would be rendered inoperative. Consequently, each of these control signals is routed to the fail-safe circuit. These control signals include, for example, tri-state and reset signals and other control signals generated by test logic circuitry for the built-in testing of the ASIC.