Abstract: A circuit is described for detecting a difference in phase and frequency between two incoming signals. Digital output signals are produced whose widths vary according to a degree of phase lead or phase lag of one signal with respect to the other. First sub-circuits are connected, one to each of the input signals to produce an output pulse of short duration, compared with a period of the incoming signal, at rising transitions of the associated input signal. Two resettable pulse detection circuits each have an output set to a first stable state when an active signal is received on a reset input and which change to a second stable state when a short duration pulse is received from one of the subcircuits on a pulse input. Further circuitry is connected such that when both outputs of the resettable pulse detection circuits are in the second stable state, an active reset signal is supplied to both resettable pulse detection circuits, to return both of their outputs to the first stable state.

Abstract: A pull-up circuit including an NPN bipolar transistor, a P-MOS transistor connected in parallel with the bipolar transistor, a first CMOS inverter for receiving an input signal and controlling the P-MOS transistor, and a second CMOS inverter for receiving the output of the first inverter and controlling the bipolar transistor. An output stage includes the pull-up circuit and also includes a pull-down circuit comprising an N-MOS transistor, a second NPN bipolar transistor connected in parallel with the N-MOS transistor, a control circuit for switching on the second NPN bipolar transistor, and a third inverter whose input is connected to the output terminal and whose output controls the N-MOS transistor and provides a signal to the control circuit for switching off the second NPN bipolar transistor.