Patents by Inventor Dawn M. Lee

Dawn M. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6607967
    Abstract: A process is disclosed for planarizing a semiconductor substrate after filling isolation trenches in the substrate with dielectric material wherein the respective thicknesses of a liner layer of dielectric material blanket deposited over the upper surface of the substrate and in the trenches, and/or a filler layer of dielectric material blanket deposited over the liner layer to fill the trenches, may not be uniform.
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: August 19, 2003
    Assignee: LSI Logic Corporation
    Inventors: Jayanthi Pallinti, Dawn M. Lee, Ronald J. Nagahara
  • Patent number: 6531397
    Abstract: Methods and apparatus for planarizing the surface of a semiconductor wafer by applying non-uniform pressure distributions across the back side of the wafer are disclosed. According to one aspect of the present invention, a chemical mechanical polishing apparatus for polishing a first surface of a semiconductor wafer includes a polishing pad which polishes the first surface of the semiconductor wafer. The apparatus also includes a first mechanism which is used to hold, or otherwise support, the wafer during polishing, and a second mechanism that is used to apply a non-uniform pressure distribution through the first mechanism, directly onto a second surface of the wafer. The second mechanism is further used to facilitate polishing the first surface of the semiconductor wafer such that the first surface of the semiconductor wafer is evenly polished.
    Type: Grant
    Filed: January 9, 1998
    Date of Patent: March 11, 2003
    Assignee: LSI Logic Corporation
    Inventors: Ronald J. Nagahara, Dawn M. Lee
  • Patent number: 6391768
    Abstract: A process-is disclosed for planarizing an integrated circuit structure by chemical mechanical polishing (CMP) after filling, with at least one metal, a plurality of trenches and/or vias formed in a silicon oxide layer on the integrated circuit structure. The process, which is capable of inhibiting formation of concave surface portions on the silicon oxide surface, during the CMP process, in regions where said trenches and/or vias are closely spaced apart, comprises forming, over a layer of silicon oxide of an integrated circuit structure, an antireflective coating (ARC) layer of dielectric material capable of functioning as a stop layer in a CMP process to remove metal; and using this ARC layer as a stop layer to assist in removal of excess metal used to fill trenches and/or vias formed in the oxide layer. The particular material chosen for the ARC layer should have a lower etch rate, in a CMP process to remove metal, than does the underlying oxide dielectric layer.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: May 21, 2002
    Assignee: LSI Logic Corporation
    Inventors: Dawn M. Lee, Jayanthi Pallinti, Weidan Li, Ming-Yi Lee
  • Patent number: 6179956
    Abstract: Methods and apparatus for planarizing the surface of a semiconductor wafer by applying non-uniform pressure distributions across the back side of the wafer are disclosed. According to one aspect of the present invention, a chemical mechanical polishing apparatus for polishing a first surface of a semiconductor wafer includes a polishing pad which polishes the first surface of the semiconductor wafer. The apparatus also includes a first mechanism which is used to hold, or otherwise support, the wafer during polishing, and a second mechanism that is used to apply a non-uniform pressure distribution through the first mechanism, directly onto a second surface of the wafer. The second mechanism is further used to facilitate polishing the first surface of the semiconductor wafer such that the first surface of the semiconductor wafer is evenly polished.
    Type: Grant
    Filed: November 16, 1999
    Date of Patent: January 30, 2001
    Assignee: LSI Logic Corporation
    Inventors: Ronald J. Nagahara, Dawn M. Lee
  • Patent number: 6168508
    Abstract: A polishing pad for chemical-mechanical polishing of an integrated circuit surface is described. The polishing pad includes a first polishing area having a first value of a physical property; and a second polishing area having a second value of said physical property, which said second value is different from the first value, such that during chemical-mechanical polishing of an integrated circuit surface, the integrated circuit rotates and oscillates on the polishing pad so that a substantial portion of the integrated circuit surface contacts both the first and second polishing areas, wherein a width of said first and second polishing areas is greater than about 40 mils.
    Type: Grant
    Filed: August 25, 1997
    Date of Patent: January 2, 2001
    Assignee: LSI Logic Corporation
    Inventors: Ronald J. Nagahara, Dawn M. Lee
  • Patent number: 6106371
    Abstract: An end effector to facilitate conditioning a surface of a polishing pad used in chemical-mechanical polishing of a substrate surface is described. The end effector includes an inwardly recessing contact surface capable of attaching to a conditioning disk having a conditioning surface such that the conditioning surface conforms to a substantial portion of the polishing pad, which protrudes outwardly under operation and thereby effectively conditions a substantial portion of the polishing pad. The present invention also describes a conditioning disk for effectively conditioning a surface of a polishing pad used in chemical-mechanical polishing of a substrate surface. The conditioning disk includes (i) a second surface capable of attaching to a contact surface of an end effector and (ii) an inwardly recessing conditioning surface that conforms to a substantial portion of said polishing pad, which protrudes outwardly under operation, and thereby effectively conditions the polishing pad.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: August 22, 2000
    Assignee: LSI Logic Corporation
    Inventors: Ronald J. Nagahara, Dawn M. Lee
  • Patent number: 6074288
    Abstract: A substrate holder assembly for forming a substantially uniformly polished substrate surface during chemical-mechanical polishing is described. The substrate holder assembly includes a carrier film having: (A) a porous layer with (i) a first surface with an outwardly protruding dome shaped region that applies pressure on at least a portion of the substrate surface during chemical-mechanical polishing and a location of the protruding dome shape is aligned with a location of an area of substrate surface that is likely to be underpolished, (ii) a second surface facing a contact surface of a backing plate; and (B) a pressure sensitive adhesive backing layer for affixing the carrier film to the contact surface of the backing plate under sufficient pressure.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: June 13, 2000
    Assignee: LSI Logic Corporation
    Inventors: Ronald J. Nagahara, Dawn M. Lee
  • Patent number: 6066266
    Abstract: A process for compensating for degradation of a first polishing pad during polishing on the first polishing pad of a plurality of substrate surfaces that have substantially similar film stacks is described. The process includes: (a) characterizing a test polishing pad, which characterization includes determining changes in film removal rates of layers of the film stack during polishing of the plurality of the substrate surfaces on the test polishing pad; (b) polishing a first substrate surface on the first polishing pad, which is substantially similar to the test polishing pad, under a first set of polishing conditions; and (c) polishing a second substrate surface on the first polishing pad under a second set of polishing conditions. A difference between the second set of polishing conditions and the first set of polishing conditions is designed to minimize the changes in the film removal rates of the layers of the film stack and thereby compensate for degradation of the first polishing pad.
    Type: Grant
    Filed: July 8, 1998
    Date of Patent: May 23, 2000
    Assignee: LSI Logic Corporation
    Inventors: Richard S. Osugi, Ronald J. Nagahara, Dawn M. Lee
  • Patent number: 6004193
    Abstract: An apparatus is provided for conditioning a polishing pad used for chemical-mechanical polishing. The apparatus comprises the retainer ring used to retain the semiconductor wafer against the polishing pad. Accordingly, the retainer ring serves a dual purpose: to retain the wafer in proper CMP position as well as condition the polishing surface while polishing of the wafer. The retainer ring includes an inner surface defining an opening to receive the semiconductor wafer. Dimensioned radially outside the inner surface is an outer surface. Placed on the distal ends between the inner and outer surfaces is an abrasive surface. The abrasive surface extends along a plane parallel to the retained frontside surface of the wafer. Both the wafer and the abrasive surface contact the polishing surface either in a rotation about a stationary axis or orbital movement about that axis.
    Type: Grant
    Filed: July 17, 1997
    Date of Patent: December 21, 1999
    Assignee: LSI Logic Corporation
    Inventors: Ron J. Nagahara, Dawn M. Lee
  • Patent number: 5961375
    Abstract: A substrate holder assembly for retaining a substrate during chemical mechanical polishing is described. The substrate holder assembly includes: (i) a backing plate including a contact surface adapted for supporting components of the substrate holder assembly and the substrate; (ii) a shim positioned adjacent the contact surface of the backing plate for applying pressure on the substrate during chemical-mechanical polishing; and (iii) a carrier film disposed adjacent the shim such that at least a portion of the carrier film adjacent the shim protrudes outwardly.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: October 5, 1999
    Assignee: LSI Logic Corporation
    Inventors: Ronald J. Nagahara, Dawn M. Lee
  • Patent number: 5944585
    Abstract: A conveying assembly in a conditioning sub-assembly for conveying a conditioning surface to a polishing pad during conditioning is described. The conveying assembly includes an arm and a guiding component connected to the arm and adapted to guide the conditioning surface about the conveying assembly, thereby allowing another area of the conditioning surface to advance and become available for conditioning.
    Type: Grant
    Filed: October 2, 1997
    Date of Patent: August 31, 1999
    Assignee: LSI Logic Corporation
    Inventors: Ronald J. Nagahara, Dawn M. Lee
  • Patent number: 5941761
    Abstract: An end effector to facilitate conditioning of a surface of a polishing pad used in chemical-mechanical polishing of an substrate surface is described. The end effector includes a rigid body including a contact surface capable of being attached to a conditioning disk and having a predetermined non-planar region that is adapted to at least one of (i) effectively maintain a non-planar area on the surface of the polishing pad and (ii) shape the polishing pad, when the end effector is employed to condition the polishing pad.
    Type: Grant
    Filed: August 25, 1997
    Date of Patent: August 24, 1999
    Assignee: LSI Logic Corporation
    Inventors: Ronald J. Nagahara, Dawn M. Lee
  • Patent number: 5931719
    Abstract: Methods and apparatus for planarizing the surface of a semiconductor wafer by applying non-uniform pressure distributions to a polishing pad are disclosed. According to one aspect of the present invention, a chemical mechanical polishing apparatus for polishing a surface of a semiconductor wafer includes a polishing pad with a first surface and a second surface. The first surface of the polishing pad is arranged to contact the surface of the semiconductor wafer in order to polish the surface of the semiconductor wafer. The apparatus also includes a mechanism which is used to apply a non-uniform pressure distribution over the second surface of the polishing pad, wherein applying the non-uniform pressure distribution to the polishing pad facilitates evenly polishing the surface of the semiconductor wafer. In one embodiment, the mechanism for applying the non-uniform pressure distribution to the polishing pad is an air bladder arrangement.
    Type: Grant
    Filed: August 25, 1997
    Date of Patent: August 3, 1999
    Assignee: LSI Logic Corporation
    Inventors: Ronald J. Nagahara, Dawn M. Lee
  • Patent number: 5816900
    Abstract: A polishing apparatus and method is disclosed, whereby fluid is delivered at dissimilar flow rates and pressures across a wafer. The fluid is delivered either directly to the wafer or through a polishing pad. Changing the fluid delivery allows the removal properties of the fluid to polish material from the wafer surface based on the location of that material relative to the center of the wafer. The fluid delivery system and the polishing pad oscillate relative to a rotating wafer. The radius of oscillation is relatively small compared to the size of the wafer to allow removal along one or more concentric rings and/or circles across the wafer.
    Type: Grant
    Filed: July 17, 1997
    Date of Patent: October 6, 1998
    Assignee: LSI Logic Corporation
    Inventors: Ron J. Nagahara, Dawn M. Lee
  • Patent number: 5769696
    Abstract: Planarization of a patterned semiconductor wafer is effected by chemical-mechanical polishing using a carrier assembly comprising a carrier film adhesively bonded to a base plate, preferably by a pressure sensitive adhesive. Chemical-mechanical polishing is preferably conducted employing three phases of different pressures to prevent wafer slippage.
    Type: Grant
    Filed: February 10, 1995
    Date of Patent: June 23, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Dawn M. Lee, Subramanian Venkatkrishnan
  • Patent number: 5766058
    Abstract: Uniform planarization of a patterned semiconductor wafer is effected with a chemical-mechanical polishing apparatus containing a base plate comprising a convex surface portion.
    Type: Grant
    Filed: January 21, 1997
    Date of Patent: June 16, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Dawn M. Lee, Subramanian Venkatkrishnan