Abstract: In an interactive display table that uses infrared (IR) light to detect an object on an interactive display surface, IR light sources within the table are controlled in response to the level of ambient IR light passing through the interactive display surface. Light from the IR light sources that is reflected the regions disposed inside the table and peripherally around the interactive display surface is captured in an image that also includes the ambient IR light passing through the interactive display surface. A signal corresponding to the image is processed, so that the relative levels of the IR light can be compared. The IR light sources are then controlled so that the level of IR light reflected from the regions exceeds the level of ambient IR light by at least a predefined amount.

Abstract: In an interactive display system, a projected image on a display surface and a vision system used to detect objects touching the display surface are aligned, and optical distortion of the vision system is compensated. Also, calibration procedures correct for a non-uniformity of infrared (IR) illumination of the display surface by IR light sources and establish a touch threshold for one or more uses so that the interactive display system correctly responds to each user touching the display surface. A movable IR camera filter enables automation of the alignment of the projected image and the image of the display surface and help in detecting problems in either the projector or vision system.

Abstract: In an interactive display system, a projected image on a display surface and a vision system used to detect objects touching the display surface are aligned, and optical distortion of the vision system is compensated. Also, calibration procedures correct for a non-uniformity of infrared (IR) illumination of the display surface by IR light sources and establish a touch threshold for one or more uses so that the interactive display system correctly responds to each user touching the display surface. A movable IR camera filter enables automation of the alignment of the projected image and the image of the display surface and help in detecting problems in either the projector or vision system.

Abstract: In an interactive display system, a projected image on a display surface and a vision system used to detect objects touching the display surface are aligned, and optical distortion of the vision system is compensated. Also, calibration procedures correct for a non-uniformity of infrared (IR) illumination of the display surface by IR light sources and establish a touch threshold for one or more uses so that the interactive display system correctly responds to each user touching the display surface. A movable IR camera filter enables automation of the alignment of the projected image and the image of the display surface and help in detecting problems in either the projector or vision system.

Abstract: An interactive display system wherein a projector receives signals from a graphics source in a manner that reduces latency in images projected onto a display surface. The signals include a pixel clock signal, pixel attribute signals, and synchronization signals. The pixel clock signal is used to clock sample and hold registers at the projector to preserve the pixel attribute signals received from the graphics source. The preserved pixel attribute signals, along with position signals corresponding to the synchronization signals, are presented directly to the projector. Parameters of the projector are known, and all gain, gamma correction, and scaling are performed before the signals are provided by the graphics source. Thus, it is unnecessary to digitize, store, adjust, or otherwise process pixel attribute signals at the projector, which simplifies processing of the graphics signals and reduces latency in generating the image in response to an input on the display surface.

Abstract: Video sensor data are communicated to a memory of a computer system with reduced latency. Upon receiving data from the video sensor, the data are stored until a desired transfer quantity is reached. The transfer quantity is equivalent to a width of a system memory or cache. When the number of data readings detected reaches an integer multiple of the transfer quantity, a bus request is issued. When the request is granted, the data readings are transferred to system memory in a burst mode. Because the transfer quantity is equivalent to a width of a system memory or cache, at least one line of memory or cache is filled during the course of the transfer. Thus, efficient use is made of bus resources. Also, because the processor can access a full line of system memory or cache without waiting for an additional fetch operation, processor resources are used efficiently.

Abstract: A printed circuit board (PCB) includes a plurality of electronic devices electrically coupled together and disposed on a first side of the PCB. The PCB also includes a rail that is connected to the underside of the PCB. This rail is configured to cooperatively engage a rail guide connected to the chassis of the computer system such that the rail guide holds the rail and the PCB to the chassis, and the PCB and rail can slide with respect to the chassis.

Abstract: Under one aspect of the invention, the invention includes a multilayered substrate. The substrate includes a primary side having a first group of connection points, including a first connection point, having a first layout to interface with a first chip. The substrate also includes a secondary side having a second group of connection points, including a second connection point, having a layout identical to the first layout, to interface with a second chip. The substrate also includes an intermediate connection point coupled to the first and second connection points through first and second branch traces each having substantially the same electrical length.

Abstract: A computer system including a chassis having a number of PCB support structures affixed thereon is disclosed. The PCB support structures are configured to support a PCB of one of a number of pre-determined lengths, employing one of a number of subset combinations of the PCB support structures. However, a constant predefined total number of fasteners is employed regardless of the length of the PCB.

Abstract: An apparatus is provided for controlling a memory refresh operation in a computer system having a processor coupled to a host volatile memory via a memory controller, a system bus controller coupled to the processor via the memory controller, and a plurality of devices coupled to the system bus controller via a system bus. The apparatus includes a first timer coupled to the memory controller for generating a first memory refresh signal at a first predetermined time interval to cause the memory controller to perform the memory refresh operation on the host volatile memory. A second timer is coupled to the system bus controller for generating a second memory refresh signal at a selective time interval to causes the system bus controller to perform the memory refresh operation on the plurality of devices. A program is provided for detecting the refresh requirement of the plurality of devices in order to determine the selective time interval.

Abstract: A computer system has a dynamically adjustable speed bus. The dynamic speed bus system decreases the length of the bus cycle accesses required for fast peripherals; but, maintains normal (longer) length bus cycles for slower peripherals. Circuitry is provided to decrease the bus cycle length by increasing the clock frequency to the bus controller which controls the bus. When accessing peripherals that can support only normal length bus cycles, the circuitry of the present invention drives the bus controller with the normal lower clock frequency. When accessing faster peripherals, a higher clock frequency is generated such that the waveform transitions smoothly between the low and high bus frequencies. The dynamic speed bus circuitry of the present invention is divided into two logic sections: 1) a decode section and 2) a clock generation section. The decode section identifies faster peripherals that are compatible with shorter bus cycles.

Abstract: A bus driver circuit having an active low-side driver and a hybrid high-side driver. When driving a logic high, the bus driver circuit delivers an active "kick" to pull the bus to a logic high state quickly and then releases the bus, allowing a weak pull-up resistor to maintain the voltage level of the bus for the remainder of the valid data phase. This kick is of limited duration, preferably lasting only long enough to bias the bus to a stable logic high while providing a remaining portion of the valid data phase that is of sufficient length for a contending bus agent to pull the bus low. The weak pull-up resistor is of sufficient size to reduce the chance that several resistors in parallel will prevent any active low-side driver of any bus agent from pulling the bus down to a low state.