Patents by Inventor De Dzwo Hsu

De Dzwo Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8766996
    Abstract: A multi-threaded processor is provided, such as a shader processor, having an internal unified memory space that is shared by a plurality of threads and is dynamically assigned to threads as needed. A mapping table that maps virtual registers to available internal addresses in the unified memory space so that thread registers can be stored in contiguous or non-contiguous memory addresses. Dynamic sizing of the virtual registers allows flexible allocation of the unified memory space depending on the type and size of data in a thread register. Yet another feature provides an efficient method for storing graphics data in the unified memory space to improve fetch and store operations from the memory space. In particular, pixel data for four pixels in a thread are stored across four memory devices having independent input/output ports that permit the four pixels to be read in a single clock cycle for processing.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: July 1, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Yun Du, Guofang Jiao, Chun Yu, De Dzwo Hsu
  • Patent number: 8654833
    Abstract: This disclosure describes efficient transformation techniques that can be used in video coding. In particular, intermediate results of computations associated with transformation of a first block of video data are reused in the transformation of a second block of video data. The techniques may be used during a motion estimation process in which video blocks of a search space are transformed, but this disclosure is not necessarily limited in this respect. Pipelining techniques may be used to accelerate the efficient transformation techniques, and transposition memories can be implemented to facilitate efficient pipelining.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: February 18, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Raghavendra C. Nagaraj, De Dzwo Hsu, Stephen Molloy
  • Patent number: 8035650
    Abstract: Caching techniques for storing instructions, constant values, and other types of data for multiple software programs are described. A cache provides storage for multiple programs and is partitioned into multiple tiles. Each tile is assignable to one program. Each program may be assigned any number of tiles based on the program's cache usage, the available tiles, and/or other factors. A cache controller identifies the tiles assigned to the programs and generates cache addresses for accessing the cache. The cache may be partitioned into physical tiles. The cache controller may assign logical tiles to the programs and may map the logical tiles to the physical tiles within the cache. The use of logical and physical tiles may simplify assignment and management of the tiles.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: October 11, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Yun Du, Guofang Jiao, Chun Yu, De Dzwo Hsu
  • Patent number: 7979684
    Abstract: A method of changing execution contexts is provided that includes receiving a context selection input. In a first clock phase, the method includes shifting data from a first latch element of a normal execution context to a second latch element of the normal execution context and shifting shadow data from a third latch element of a shadow execution context to a fourth latch element of the shadow execution context. In a second clock phase, the method includes shifting the shadow data of the fourth latch element of the shadow execution context into the first latch element of the normal execution context and shifting the data of the second latch element of the normal execution context into the third latch element of the shadow execution context. In a particular embodiment, the method may include receiving a test mode selection and shifting test data, such as scan test or automatic test pattern generated data, to a test output.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: July 12, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Jentsung Lin, Eai-Hsin Alfred Kuo, De Dzwo Hsu
  • Patent number: 7912279
    Abstract: Automatic white balance of captured images can be performed based on a gray world assumption. One aspect relates to an apparatus comprising a collection module and a processor. The collection module is configured to accumulate (a) red/green and blue/green color ratio values of a plurality of pixels in a captured image for each cluster of a plurality of clusters and (b) a number of pixels having red/green and blue/green color ratios associated with each cluster, the clusters comprising daylight, fluorescent, incandescent, and a outdoor green zone. The processor is configured to determine which cluster has a highest accumulated number of pixels, and use the cluster with the highest accumulated number of pixels to perform white balancing for the captured image.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: March 22, 2011
    Assignee: Qualcomm Incorporated
    Inventors: De Dzwo Hsu, Hsiang-Tsun Li, Szepo Robert Hung
  • Publication number: 20090080515
    Abstract: This disclosure describes efficient transformation techniques that can be used in video coding. In particular, intermediate results of computations associated with transformation of a first block of video data are reused in the transformation of a second block of video data. The techniques may be used during a motion estimation process in which video blocks of a search space are transformed, but this disclosure is not necessarily limited in this respect. Pipelining techniques may be used to accelerate the efficient transformation techniques, and transposition memories can be implemented to facilitate efficient pipelining.
    Type: Application
    Filed: September 26, 2007
    Publication date: March 26, 2009
    Applicant: QUALCOMM Incorporated
    Inventors: Raghavendra C. Nagaraj, De Dzwo Hsu, Stephen Molloy
  • Publication number: 20080101690
    Abstract: Automatic white balance of captured images can be performed based on a gray world assumption. One aspect relates to an apparatus comprising a collection module and a processor. The collection module is configured to accumulate (a) red/green and blue/green color ratio values of a plurality of pixels in a captured image for each cluster of a plurality of clusters and (b) a number of pixels having red/green and blue/green color ratios associated with each cluster, the clusters comprising daylight, fluorescent, incandescent, and a outdoor green zone. The processor is configured to determine which cluster has a highest accumulated number of pixels, and use the cluster with the highest accumulated number of pixels to perform white balancing for the captured image.
    Type: Application
    Filed: October 26, 2006
    Publication date: May 1, 2008
    Inventors: De Dzwo Hsu, Hsiang-Tsun Li, Szepo Robert Hung
  • Publication number: 20080034192
    Abstract: A method of changing execution contexts is provided that includes receiving a context selection input. In a first clock phase, the method includes shifting data from a first latch element of a normal execution context to a second latch element of the normal execution context and shifting shadow data from a third latch element of a shadow execution context to a fourth latch element of the shadow execution context. In a second clock phase, the method includes shifting the shadow data of the fourth latch element of the shadow execution context into the first latch element of the normal execution context and shifting the data of the second latch element of the normal execution context into the third latch element of the shadow execution context. In a particular embodiment, the method may include receiving a test mode selection and shifting test data, such as scan test or automatic test pattern generated data, to a test output.
    Type: Application
    Filed: August 7, 2006
    Publication date: February 7, 2008
    Inventors: Jentsung Lin, Eai-Hsin Alfred Kuo, De Dzwo Hsu
  • Publication number: 20080028152
    Abstract: Caching techniques for storing instructions, constant values, and other types of data for multiple software programs are described. A cache provides storage for multiple programs and is partitioned into multiple tiles. Each tile is assignable to one program. Each program may be assigned any number of tiles based on the program's cache usage, the available tiles, and/or other factors. A cache controller identifies the tiles assigned to the programs and generates cache addresses for accessing the cache. The cache may be partitioned into physical tiles. The cache controller may assign logical tiles to the programs and may map the logical tiles to the physical tiles within the cache. The use of logical and physical tiles may simplify assignment and management of the tiles.
    Type: Application
    Filed: July 25, 2006
    Publication date: January 31, 2008
    Inventors: Yun Du, Guofang Jiao, Chun Yu, De Dzwo Hsu
  • Publication number: 20070296729
    Abstract: A multi-threaded processor is provided, such as a shader processor, having an internal unified memory space that is shared by a plurality of threads and is dynamically assigned to threads as needed. A mapping table that maps virtual registers to available internal addresses in the unified memory space so that thread registers can be stored in contiguous or non-contiguous memory addresses. Dynamic sizing of the virtual registers allows flexible allocation of the unified memory space depending on the type and size of data in a thread register. Yet another feature provides an efficient method for storing graphics data in the unified memory space to improve fetch and store operations from the memory space. In particular, pixel data for four pixels in a thread are stored across four memory devices having independent input/output ports that permit the four pixels to be read in a single clock cycle for processing.
    Type: Application
    Filed: June 21, 2006
    Publication date: December 27, 2007
    Inventors: Yun Du, Guofang Jiao, Chun Yu, De Dzwo Hsu
  • Patent number: 6975362
    Abstract: A VGA to analog video converter is useful e.g. for displaying video and/or graphics data from a computer onto a large screen television or television monitor. The RGB video signals output from the personal computer are first converted to digital form. The analog-to-digital converter which does this is clocked by a clock signal generated by a phase-locked loop using the horizontal synchronizing signal from the personal computer. The digital RGB signals are then converted to a YCbCR format. A flicker filter eliminates the flickering appearing on the TV monitor by operating on the luminance (Y) component. The YCbCr signals are encoded into NTSC or PAL Standard, and output in composite analog video or S-VHS format. A color subcarrier synthesizer generates the color subcarrier signal to generate an accurate subcarrier frequency for the video output signals. An analog-to-digital clock phase adjustment is used to ensure that the input RGB signals are sampled at the proper instant by the analog-to-digital converters.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: December 13, 2005
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Mehdi H. Sani, De Dzwo Hsu, Willard K. Bucklen
  • Publication number: 20030020830
    Abstract: A VGA to analog video converter is useful e.g. for displaying video and/or graphics data from a computer onto a large screen television or television monitor. The RGB video signals output from the personal computer are first converted to digital form. The analog-to-digital converter which does this is clocked by a clock signal generated by a phase-locked loop using the horizontal synchronizing signal from the personal computer. The digital RGB signals are then converted to a YCbCR format. A flicker filter eliminates the flickering appearing on the TV monitor by operating on the luminance (Y) component. The YCbCr signals are encoded into NTSC or PAL Standard, and output in composite analog video or S-VHS format. A color subcarrier synthesizer generates the color subcarrier signal to generate an accurate subcarrier frequency for the video output signals. An analog-to-digital clock phase adjustment is used to ensure that the input RGB signals are sampled at the proper instant by the analog-to-digital converters.
    Type: Application
    Filed: May 13, 2002
    Publication date: January 30, 2003
    Inventors: Mehdi H. Sani, De Dzwo Hsu, Willard K. Bucklen
  • Patent number: 6429904
    Abstract: A VGA to analog video converter is useful e.g. for displaying video and/or graphics data from a computer onto a large screen television or television monitor. The RGB video signals output from the personal computer are first converted to digital form. The analog-to-digital converter which does this is clocked by a clock signal generated by a phase-locked loop using the horizontal synchronizing signal from the personal computer. The digital RGB signals are then converted to a YCbCR format. A flicker filter eliminates the flickering appearing on the TV monitor by operating on the luminance (Y) component. The YCbCr signals are encoded into NTSC or PAL Standard, and output in composite analog video or S-VHS format. A color subcarrier synthesizer generates the color subcarrier signal to generate an accurate subcarrier frequency for the video output signals. An analog-to-digital clock phase adjustment is used to ensure that the input RGB signals are sampled at the proper instant by the analog-to-digital converters.
    Type: Grant
    Filed: February 13, 2001
    Date of Patent: August 6, 2002
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Mehdi H. Sani, De Dzwo Hsu, Willard K. Bucklen
  • Publication number: 20010017666
    Abstract: A VGA to analog video converter is useful e.g. for displaying video and/or graphics data from a computer onto a large screen television or television monitor. The RGB video signals output from the personal computer are first converted to digital form. The analog-to-digital converter which does this is clocked by a clock signal generated by a phase-locked loop using the horizontal synchronizing signal from the personal computer. The digital RGB signals are then converted to a YCbCR format. A flicker filter eliminates the flickering appearing on the TV monitor by operating on the luminance (Y) component. The YCbCr signals are encoded into NTSC or PAL Standard, and output in composite analog video or S-VHS format. A color subcarrier synthesizer generates the color subcarrier signal to generate an accurate subcarrier frequency for the video output signals. An analog-to-digital clock phase adjustment is used to ensure that the input RGB signals are sampled at the proper instant by the analog-to-digital converters.
    Type: Application
    Filed: February 13, 2001
    Publication date: August 30, 2001
    Inventors: Mehdi H. Sani, De Dzwo Hsu, Willard K. Bucklen
  • Patent number: 6219101
    Abstract: A VGA to analog video converter is useful e.g. for displaying video and/or graphics data from a computer onto a large screen television or television monitor. The RGB video signals output from the personal computer are first converted to digital form. The analog-to-digital converter which does this is clocked by a clock signal generated by a phase-locked loop using the horizontal synchronizing signal from the personal computer. The digital RGB signals are then converted to a YCbCR format. A flicker filter eliminates the flickering appearing on the TV monitor by operating on the luminance (Y) component. The YCbCr signals are encoded into NTSC or PAL Standard, and output in composite analog video or S-VHS format. A color subcarrier synthesizer generates the color subcarrier signal to generate an accurate subcarrier frequency for the video output signals. An analog-to-digital clock phase adjustment is used to ensure that the input RGB signals are sampled at the proper instant by the analog-to-digital converters.
    Type: Grant
    Filed: May 15, 1998
    Date of Patent: April 17, 2001
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Mehdi H. Sani, De Dzwo Hsu, Willard K. Bucklen
  • Patent number: 5786866
    Abstract: A color subcarrier signal generator for use e.g, in a video converter measures the average error of the horizontal synchronizing signal frequency. The measured error is used as a compensator signal to control a direct digital synthesizer to generate a correct color subcarrier signal. The direct digital frequency synthesizer includes an address generator receiving the error signal and a look up table driven by the address generator.
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: July 28, 1998
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Mehdi H. Sani, De Dzwo Hsu, Willard K. Bucklen