Abstract: An audio playback system that includes audio playback devices each including a communication module, a playback module and a processing module is provided. The communication module receives a beacon signal and audio signal packets and generates an interrupt signal. The processing module receives the interrupt signal to retrieve an audio source timestamp corresponding to an audio source system time from the beacon signal, compares the audio source timestamp with an internal time generated based on an internal system time when the beacon signal is received to calculate a difference therebetween, receives a playback initialization signal from the audio source device that includes an audio source system playback initialization time, calculates an internal system playback initialization time according to the difference and the audio source system playback initialization time and controls the playback module to playback the audio signal packets from the internal system playback initialization time.

Abstract: A hex wrench improved structure comprises a body, one end thereof has six equally divided planes, an abutting angle is formed between each of the two planes, at least one of the planes is disposed with a groove, the groove has two inclined surfaces, one side of each of the two inclined surfaces is connected to the abutting angle of the two planes, another sides of the two inclined surfaces are connected to each other, and an obtuse angle is included between the two inclined surfaces; thereby, the hex wrench can be pressed tightly against an inner wall surface of a hole in a screw for inserting a cap screw tool to apply force, so that the hex wrench is not easy to slip, and it is easier to turn and lock or adjust the screw.

Abstract: Present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate, forming a first III-V compound layer over the substrate, forming a first passivation layer over the first III-V compound layer, forming a first opening from a top surface of the first passivation layer to the first III-V compound layer, each opening having a stair-shaped sidewall at the first passivation layer, depositing a metal layer over the first passivation layer and in the first opening, the metal layer having a second opening above the corresponding first opening, and removing a portion of the metal layer to form a source electrode and a drain electrode.

Abstract: Present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate, forming a first III-V compound layer over the substrate, forming a first passivation layer over the first III-V compound layer, forming a first opening from a top surface of the first passivation layer to the first III-V compound layer, each opening having a stair-shaped sidewall at the first passivation layer, depositing a metal layer over the first passivation layer and in the first opening, the metal layer having a second opening above the corresponding first opening, and removing a portion of the metal layer to form a source electrode and a drain electrode.

Abstract: A multi-link convergence method include: receiving a first binding request sent by a client using a first link; sending a first LSID to the client using the first link; receiving a first authentication request sent by the client using the first link; performing authentication on the first link according to the first authentication request; if the first link is authenticated successfully, sending a BID to the client using the first link; receiving a second binding request sent by the client using a second link, where the second binding request carries the BID; sending a second LSID to the client using the second link; receiving a second authentication request sent the client by using the second link; performing authentication on the second link according to the second authentication request; and if the second link is authenticated successfully, sending a binding acknowledgement message to the client using the second link.

Abstract: A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.

Abstract: A multicast delay diagnosis method is provided, where the method includes sending, by a terminal device, a first domain name resolution request to a network node; receiving a first multicast test address returned by the network node; sending a first multicast test join request to the network node by using the first multicast test address, and recording a time point for sending the first multicast test join request; receiving a first packet returned by the network node, and recording a time point for receiving the first packet; calculating, according to the time point for sending the first multicast test join request and the time point for receiving the first packet, a first delay caused when the terminal device joins a multicast test group of the network node; and determining multicast network quality according to the first delay.

Abstract: A semiconductor structure includes a semiconductive substrate having a top surface, a III-V compound layer covering the top surface, and a passivation layer having a lower portion and an upper portion, both comprising at least one of oxide and nitride over the III-V compound layer. The semiconductor structure also includes an etch stop layer between the lower portion and the upper portion of the passivation layer, and a gate stack penetrating through the etch stop layer and landing on the lower portion of the passivation layer. The gate stack is surrounded by the etch stop layer.

Abstract: Present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate, forming a first III-V compound layer over the substrate, forming a first passivation layer over the first III-V compound layer, forming a first opening from a top surface of the first passivation layer to the first III-V compound layer, each opening having a stair-shaped sidewall at the first passivation layer, depositing a metal layer over the first passivation layer and in the first opening, the metal layer having a second opening above the corresponding first opening, and removing a portion of the metal layer to form a source electrode and a drain electrode.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a first III-V compound layer over the substrate, a first passivation layer on the first III-V compound layer, a source region and a drain region. The source region penetrates the first passivation layer to electrically contact the first III-V compound layer. The drain region penetrates the first passivation layer to electrically contact the first III-V compound layer. A sidewall of the first passivation layer contacting with the source region comprises a stair shape.

Abstract: A semiconductor structure includes a semiconductive substrate having a top surface, a III-V compound layer covering the top surface, and a passivation layer having a lower portion and an upper portion, both comprising at least one of oxide and nitride over the III-V compound layer. The semiconductor structure also includes an etch stop layer between the lower portion and the upper portion of the passivation layer, and a gate stack penetrating through the etch stop layer and landing on the lower portion of the passivation layer. The gate stack is surrounded by the etch stop layer.

Abstract: IPv6 address assignment method and apparatus are provided. The method includes: receiving first Prefix Delegations (PDs) sent by at least two network access devices, where the first PDs sent by the different network access devices are different from each other; generating second PDs according to the received first PDs, where the second PDs have a one-to-one correspondence with the first PDs; and sending the generated second PDs to user device for generating by the user device IPv6 addresses according to the second PDs.

Abstract: A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.

Abstract: A semiconductor structure comprises a semiconductive substrate comprising a top surface, a III-V compound layer over the semiconductive substrate, and a first passivation layer over the III-V compound layer. The semiconductor structure also includes an etch stop layer over the first passivation layer. The semiconductor structure further includes a gate stack over the first passivation layer and surrounded by the etch stop layer.

Abstract: A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.

Abstract: A multi-link convergence method include: receiving a first binding request sent by a client using a first link; sending a first LSID to the client using the first link; receiving a first authentication request sent by the client using the first link; performing authentication on the first link according to the first authentication request; if the first link is authenticated successfully, sending a BID to the client using the first link; receiving a second binding request sent by the client using a second link, where the second binding request carries the BID; sending a second LSID to the client using the second link; receiving a second authentication request sent the client by using the second link; performing authentication on the second link according to the second authentication request; and if the second link is authenticated successfully, sending a binding acknowledgement message to the client by using the second link.

Abstract: A semiconductor structure comprises a semiconductive substrate comprising a top surface, a III-V compound layer over the semiconductive substrate, and a first passivation layer over the III-V compound layer. The semiconductor structure also includes an etch stop layer over the first passivation layer. The semiconductor structure further includes a gate stack over the first passivation layer and surrounded by the etch stop layer.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a first III-V compound layer over the substrate, a first passivation layer on the first III-V compound layer, a source region and a drain region. The source region penetrates the first passivation layer to electrically contact the first III-V compound layer. The drain region penetrates the first passivation layer to electrically contact the first III-V compound layer. A sidewall of the first passivation layer contacting with the source region comprises a stair shape.

Abstract: Embodiments of the present disclosure include a MISFET device. An embodiment includes a source/drain over a substrate, a first etch stop layer on the source/drain, and a gate dielectric layer on the first etch stop layer and along the substrate. The embodiment also includes a gate electrode on the gate dielectric layer, and a second etch stop layer on the gate electrode.