Patents by Inventor De Lu
De Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240102966Abstract: A detection method based on a battery defect detection system, a system and a storage medium are disclosed. The detection method includes: acquiring a scanning trigger signal, and controlling an ultrasonic transceiver and a motion control platform to work, so that the ultrasonic transceiver receives waveform data of ultrasonic waves passing through a cell; controlling an oscilloscope to collect the waveform data; receiving the waveform data and performing imaging processing to obtain an imaging diagram; and detecting whether or not the cell has a defect according to the imaging diagram.Type: ApplicationFiled: November 14, 2022Publication date: March 28, 2024Inventors: De Chen, Qihui Lu, Peng Fan
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Publication number: 20240087799Abstract: An inductor device including a frame portion, a first winding set, a second winding set and a first common magnetic core I piece is provided. The first winding set, the second winding set and the first common magnetic core I piece are disposed in the frame portion. The first common magnetic core I piece substantially connects the first winding set and the second winding set and the frame portion. The material of the two winding sets is different from that of the first common magnetic core I piece.Type: ApplicationFiled: November 21, 2022Publication date: March 14, 2024Inventors: Kai-De CHEN, Yong-Long SYU, Chen CHEN, De-Jia LU, Chao-Lin CHUNG
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Patent number: 11823962Abstract: Aspects of the disclosure are directed to sensing integrated circuit (IC) Back End Of Line (BEOL) process corners. In one aspect, an apparatus for sensing IC BEOL process corners includes a ring oscillator including a plurality of ring oscillator stages configured to generate an output waveform with a frequency state; and a shield net circuit including a plurality of shield net stages corresponding to the plurality of ring oscillator stages, the shield net circuit having a toggle input. And, a method includes generating an output waveform with a frequency state using a ring oscillator that includes a plurality of ring oscillator stages; modifying a plurality of ring oscillator stage time delays through a coupling between a plurality of shield net stages and the plurality of ring oscillator stages; and selecting the frequency state using a toggle input of a shield net circuit which includes the plurality of shield net stages.Type: GrantFiled: February 19, 2021Date of Patent: November 21, 2023Assignee: QUALCOMM INCORPORATEDInventors: Saravanan Marimuthu, De Lu, Baldeo Sharan Sharma, Peeyush Kumar Parkar, Venkat Narayanan, Rui Li, Samy Shafik Tawfik Zaynoun, Min Chen, David Kidd, Amit Patil
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Patent number: 11810636Abstract: An aspect of the disclosure relates to a latch array, including: a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a first set of data, and a first set of data outputs coupled to a set of bitlines, respectively; a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write-bit inputs configured to receive a set of write-bit signals, and a set of write-bit outputs coupled to a set of write-bit lines, respectively; and an array of slave latches, wherein the slave latches in columns of the array include a second set of data inputs coupled to the set of bitlines, and a second set of write-bit inputs coupled to the set of write-bit lines, respectively.Type: GrantFiled: January 12, 2022Date of Patent: November 7, 2023Assignee: QUALCOMM INCORPORATEDInventors: Rui Li, De Lu, Venkat Narayanan
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Publication number: 20230223054Abstract: An aspect of the disclosure relates to a latch array, including: a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a first set of data, and a first set of data outputs coupled to a set of bitlines, respectively; a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write-bit inputs configured to receive a set of write-bit signals, and a set of write-bit outputs coupled to a set of write-bit lines, respectively; and an array of slave latches, wherein the slave latches in columns of the array include a second set of data inputs coupled to the set of bitlines, and a second set of write-bit inputs coupled to the set of write-bit lines, respectively.Type: ApplicationFiled: January 12, 2022Publication date: July 13, 2023Inventors: Rui LI, De LU, Venkat NARAYANAN
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Patent number: 11695393Abstract: A latch array including a row of master latches coupled to columns of slave latches. Each master latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch an input data, and each slave latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch the data from the master latch, and an inverter including an input coupled to the AOI gate and an output to produce an output data based on the input data. Alternatively, each master latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch an input data, and each slave latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch the data from the master latch, and an inverter including an input coupled to the OAI gate and an output to produce an output data.Type: GrantFiled: January 29, 2021Date of Patent: July 4, 2023Assignee: QUALCOMM INCORPORATEDInventors: Rui Li, De Lu, Venkat Narayanan
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Publication number: 20220270938Abstract: Aspects of the disclosure are directed to sensing integrated circuit (IC) Back End Of Line (BEOL) process corners. In one aspect, an apparatus for sensing IC BEOL process corners includes a ring oscillator including a plurality of ring oscillator stages configured to generate an output waveform with a frequency state; and a shield net circuit including a plurality of shield net stages corresponding to the plurality of ring oscillator stages, the shield net circuit having a toggle input. And, a method includes generating an output waveform with a frequency state using a ring oscillator that includes a plurality of ring oscillator stages; modifying a plurality of ring oscillator stage time delays through a coupling between a plurality of shield net stages and the plurality of ring oscillator stages; and selecting the frequency state using a toggle input of a shield net circuit which includes the plurality of shield net stages.Type: ApplicationFiled: February 19, 2021Publication date: August 25, 2022Inventors: Saravanan MARIMUTHU, De LU, Baldeo Sharan SHARMA, Peeyush Kumar PARKAR, Venkat NARAYANAN, Rui LI, Samy Shafik Tawfik ZAYNOUN, Min CHEN, David KIDD, Amit PATIL
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Publication number: 20220247391Abstract: A latch array including a row of master latches coupled to columns of slave latches. Each master latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch an input data, and each slave latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch the data from the master latch, and an inverter including an input coupled to the AOI gate and an output to produce an output data based on the input data. Alternatively, each master latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch an input data, and each slave latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch the data from the master latch, and an inverter including an input coupled to the OAI gate and an output to produce an output data.Type: ApplicationFiled: January 29, 2021Publication date: August 4, 2022Inventors: Rui LI, De LU, Venkat NARAYANAN
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Patent number: 11334321Abstract: A true random number generator (TRNG) for generating a sequence of random numbers of bits is disclosed. The TRNG includes a TRNG cell configured to generate a sequence of bits logically alternating with a mean frequency and with substantially random period jitter; a period monitor configured to generate a first sequence of random bits based on a set of periods of the sequence of logically alternating bits; and a sampling circuit configured to sample the first sequence of random bits in response to a sampling clock to generate a second sequence of random bits.Type: GrantFiled: June 26, 2020Date of Patent: May 17, 2022Assignee: QUALCOMM INCORPORATEDInventors: Rui Li, De Lu, Venkat Narayanan, Srivatsan Chellappa
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Publication number: 20220021578Abstract: A method for configuring modeling parameters, an electronic device and a computer storage medium, which relate to the field of artificial intelligence and deep learning technologies, are disclosed. An association rule among modeling parameters is hidden in an interaction, and the user is guided to complete a configuration of the modeling parameters in the form of a page interaction.Type: ApplicationFiled: March 22, 2021Publication date: January 20, 2022Inventors: De Lu, Mingzhi Xu
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Publication number: 20210405973Abstract: A true random number generator (TRNG) for generating a sequence of random numbers of bits is disclosed. The TRNG includes a TRNG cell configured to generate a sequence of bits logically alternating with a mean frequency and with substantially random period jitter; a period monitor configured to generate a first sequence of random bits based on a set of periods of the sequence of logically alternating bits; and a sampling circuit configured to sample the first sequence of random bits in response to a sampling clock to generate a second sequence of random bits.Type: ApplicationFiled: June 26, 2020Publication date: December 30, 2021Inventors: Rui LI, De LU, Venkat NARAYANAN, Srivatsan CHELLAPPA
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Patent number: 10987909Abstract: The present invention provides a method of laminating a film for a dye-sensitized cell. First, a composite film is taken by a robotic arm, in which the composite film includes a release layer, a protective layer and a hot glue layer between the release layer and the protective layer, and the release layer is removed by the robotic arm. Then, the hot glue layer is precisely attached to a substrate by a target positioning step. Next, the protective layer is removed by the robotic arm.Type: GrantFiled: October 2, 2019Date of Patent: April 27, 2021Assignee: FORMOSA PLASTICS CORPORATIONInventors: Ching-Fu Chen, Hao-Wei Chen, Kun-Tai Ho, Wan-Tun Hung, Po-Min Chen, Liang-Kun Huang, Chih-Chou Chang, Yung-Liang Tung, Po-Tsung Hsiao, Ming-De Lu
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Publication number: 20200101711Abstract: The present invention provides a method of laminating a film for a dye-sensitized cell. First, a composite film is taken by a robotic arm, in which the composite film includes a release layer, a protective layer and a hot glue layer between the release layer and the protective layer, and the release layer is removed by the robotic arm. Then, the hot glue layer is precisely attached to a substrate by a target positioning step. Next, the protective layer is removed by the robotic arm.Type: ApplicationFiled: October 2, 2019Publication date: April 2, 2020Inventors: Ching-Fu CHEN, Hao-Wei CHEN, Kun-Tai HO, Wan-Tun HUNG, Po-Min CHEN, Liang-Kun HUANG, Chih-Chou CHANG, Yung-Liang TUNG, Po-Tsung HSIAO, Ming-De LU
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Patent number: 10164768Abstract: In certain aspects, a circuit includes a dynamic differential logic gate having first and second outputs, and a first static differential logic gate having first and second outputs, and first and second inputs coupled to the first and second outputs, respectively, of the dynamic differential logic gate. The dynamic differential logic gate is configured to receive a clock signal and to preset both the first and second outputs of the dynamic differential logic gate to a first preset value during a first phase of the clock signal. The first static differential logic gate is configured to preset both the first and second outputs of the first static differential logic gate to a second preset value when the first preset value is input to both the first and second inputs of the first static differential logic gate.Type: GrantFiled: February 23, 2018Date of Patent: December 25, 2018Assignee: QUALCOMM IncorporatedInventors: Ravindraraj Ramaraju, Rakesh Vattikonda, Samrat Sinharoy, De Lu, Bo Pang
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Publication number: 20180174623Abstract: An apparatus and method are disclosed for transferring data from a first core to a second core of an integrated circuit (IC). The first core includes first and second memory blocks (e.g., first and second portions of a first-in-first-out (FIFO) memory coupled to first and second pre-multiplexers, respectively). The second core includes a multiplexer including first and second inputs coupled to the first and second memory blocks, respectively. Additionally, the second core includes a read controller configured to generate a first read control signal to cause the first and second memory blocks to transfer data to the first and second inputs of the multiplexer, respectively; and generate a second read control signal to cause the multiplexer to transfer data from the first and inputs to an output of the multiplexer.Type: ApplicationFiled: December 16, 2016Publication date: June 21, 2018Inventors: Fei Xu, Rakesh Vattikonda, Dina McKinney, Zhen Chen, Yun Li, Zhenbiao Ma, De Lu
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Patent number: 9948303Abstract: In one embodiment, a voltage level shifter includes a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain, and a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node. The voltage level shifter also includes an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor, and a first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground.Type: GrantFiled: December 2, 2016Date of Patent: April 17, 2018Assignee: QUALCOMM IncorporatedInventors: Venkat Narayanan, Rakesh Vattikonda, De Lu, Ramaprasath Vilangudipitchai, Samrat Sinharoy, Rui Chen
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Patent number: 9941866Abstract: In an aspect of the disclosure, a method and an apparatus are provided. The apparatus is a register array including first and second flip-flop latch arrays. The first flip-flop latch array includes a first set of master latches, a first set of slave latches coupled to the first set of master latches, and a first address port. The second flip-flop latch array includes a second set of master latches, a second set of slave latches coupled to the second set of master latches, and a second address port. The register array includes an address counter, coupled to the first flip-flop latch array and the second flip-flop latch array. The address counter is shared by the first flip-flop latch array and the second flip-flop latch array and configured to address, in parallel in a test mode, the first flip-flop latch array through the first address port and the second flip-flop latch array through the second address port.Type: GrantFiled: July 12, 2016Date of Patent: April 10, 2018Assignee: QUALCOMM IncorporatedInventors: Rakesh Vattikonda, Samrat Sinharoy, De Lu
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Publication number: 20180074126Abstract: An apparatus and method of employing mutually exclusive write and read clocks in scan capture mode for testing digital interfaces. The apparatus includes a first circuit and a first clock generator configured to generate a first clock signal for transferring a test sample from an input to an output of the first circuit in response to the first clock signal during each of a first set of scan capture cycles; a second circuit and a second clock generator configured to generate a second clock signal for transferring the test sample from an input to an output of the second circuit in response to the second clock signal during each of a second set of scan capture cycle; the first clock signal being suppressed during each scan capture cycle of the second set, and the second clock signal being suppressed during each scan capture cycle of the first set.Type: ApplicationFiled: September 12, 2016Publication date: March 15, 2018Inventors: Bilal Zafar, Rakesh Vattikonda, De Lu, Venkatasubramanian Narayanan, Masoud Zamani, Joseph Fang
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Publication number: 20180019734Abstract: In an aspect of the disclosure, a method and an apparatus are provided. The apparatus is a register array including first and second flip-flop latch arrays. The first flip-flop latch array includes a first set of master latches, a first set of slave latches coupled to the first set of master latches, and a first address port. The second flip-flop latch array includes a second set of master latches, a second set of slave latches coupled to the second set of master latches, and a second address port. The register array includes an address counter, coupled to the first flip-flop latch array and the second flip-flop latch array. The address counter is shared by the first flip-flop latch array and the second flip-flop latch array and configured to address, in parallel in a test mode, the first flip-flop latch array through the first address port and the second flip-flop latch array through the second address port.Type: ApplicationFiled: July 12, 2016Publication date: January 18, 2018Inventors: Rakesh VATTIKONDA, Samrat SINHAROY, De LU
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Publication number: 20180006651Abstract: In one embodiment, a voltage level shifter includes a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain, and a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node. The voltage level shifter also includes an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor, and a first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground.Type: ApplicationFiled: December 2, 2016Publication date: January 4, 2018Inventors: Venkat Narayanan, Rakesh Vattikonda, De Lu, Ramaprasath Vilangudipitchai, Samrat Sinharoy, Rui Chen