Abstract: A micro light-emitting device, including a first type semiconductor layer, a light-emitting layer, a second type semiconductor layer, a first type electrode, a second type electrode, and a light reflection layer, is provided. The light-emitting layer is arranged on the first type semiconductor layer. The second type semiconductor layer is arranged on the light-emitting layer. The first type electrode and the second type electrode are both arranged on the second type semiconductor layer. The light reflection layer is arranged between the light-emitting layer and the first type electrode. The light reflection layer includes an oxidized area and a non-oxidized area. A reflectance of the oxidized area is greater than a reflectance of the non-oxidized area. An orthographic projection of a part of the oxidized area on the first type semiconductor layer and an orthographic projection of the first type electrode on the first type semiconductor layer at least partially overlap.

Abstract: Embodiments of the present application disclose an adhesive, a die attach film and a preparation method therefor, and relate to the technical field of chip packaging. The adhesive includes epoxy resin, phenoxy resin, an indene oligomer, filler and a curing agent; and 20-60 parts of the epoxy resin, 20-30 parts of the phenoxy resin, 5-10 parts of the indene oligomer, 15-30 parts of the filler and 1-5 parts of the curing agent are provided in parts by mass. The present application further provides the die attach film and the preparation method therefor. In the adhesive provided by the present application, the epoxy resin, the phenoxy resin and the indene oligomer are used as curable substrates to improve a thermal stress obtained after the adhesive is cured, so that the die attach film prepared therefrom is not easy to warp in a temperature change process.

Abstract: A micro light-emitting diode includes a first stacked layer, a second stacked layer, a third stacked layer, a bonding layer, at least one etch stop layer, and a plurality of electrodes. The second stacked layer is disposed between the first stacked layer and the third stacked layer. The first stacked layer includes a first active layer. The second stacked layer includes a second active layer. The third stacked layer includes a third active layer. The bonding layer is disposed between the second stacked layer and the third stacked layer. The at least one etch stop layer is at least disposed between the first active layer and the second active layer. The plurality of electrodes are respectively electrically connected with the first stacked layer, the second stacked layer, and the third stacked layer. At least one electrode of the plurality of electrodes contacts the etch stop layer.

Abstract: A semiconductor device includes a gate structure, source/drain regions, source/drain contacts, a gate dielectric cap, an etch stop layer, and a gate contact. The gate structure is over a substrate. The source/drain regions are at opposite sides of the gate structure. The source/drain contacts are over the source/drain regions, respectively. The gate dielectric cap is over the gate structure and has opposite sidewalls interfacing the source/drain contacts.

Abstract: A high-glossiness epoxy molding compound (EMC) film for protecting a chip and a preparation method thereof are disclosed. The high-glossiness EMC film for protecting a chip includes: 40 to 100 parts by mass of an epoxy resin; 2 to 5 parts by mass of glass epoxy; 45 to 55 parts by mass of fused silica; and 1 to 5 parts by mass of a curing system, where the fused silica has a particle size D50 of 0.15 ?m to 0.6 ?m. The glossiness of the protective film of the present disclosure is significantly improved, such that the clarity of characters inscribed by a laser under a bright field of a microscope can be further improved, which allows a device to effectively recognize the characters.

Abstract: A method comprises forming a source/drain contact over a source/drain region; forming an etch stop layer over the source/drain contact and an interlayer dielectric (ILD) layer over the etch stop layer; performing a first etching process to form a via opening extending through the ILD layer and a recess in the etch stop layer; oxidizing a sidewall of the recess in the etch stop layer; after oxidizing the sidewall of the recess in the etch stop layer, performing a second etching process to extend the via opening down to the source/drain contact; and after performing the second etching process, forming a source/drain via in the via opening.

Abstract: Embodiments of the present application disclose an adhesive, a die attach film and a preparation method therefor, and relate to the technical field of chip packaging. The adhesive includes epoxy resin, phenoxy resin, an indene oligomer, filler and a curing agent; and 20-60 parts of the epoxy resin, 20-30 parts of the phenoxy resin, 5-10 parts of the indene oligomer, 15-30 parts of the filler and 1-5 parts of the curing agent are provided in parts by mass. The present application further provides the die attach film and the preparation method therefor. In the adhesive provided by the present application, the epoxy resin, the phenoxy resin and the indene oligomer are used as curable substrates to improve a thermal stress obtained after the adhesive is cured, so that the die attach film prepared therefrom is not easy to warp in a temperature change process.

Abstract: The present application discloses an underfill for chip packaging, including 19-25% of epoxy resin, 55-60% of filler, 15-25% of curing agent and 0.5-0.8% of accelerator in mass percentage, wherein the curing agent includes a polycondensate of paraxylene and dihydroxynaphthalene and a polycondensate of paraxylene and naphthol. Both of the polycondensate of paraxylene and dihydroxynaphthalene and the polycondensate of paraxylene and naphthol are selected to be used in the underfill for chip packaging in the present application, so that the underfill has stronger adhesiveness after being cured. In addition, the present application further provides a chip packaging structure using the underfill.

Abstract: A method includes depositing a dielectric cap over a gate structure. A source/drain contact is formed over a source/drain region after forming the dielectric cap. A top of the dielectric cap is doped to form a doped region in the dielectric cap. After doping the top of the dielectric cap, a etch stop layer and an interlayer dielectric (ILD) layer are deposited over the dielectric cap. A via opening is formed to extend though the ILD layer and the etch stop layer to expose the source/drain contact. A source/drain via is filled in the via opening.

Abstract: A method comprises forming a gate structure over a semiconductor substrate; etching back the gate structure; forming a gate dielectric cap over the etched back gate structure; depositing an etch-resistant layer over the gate dielectric cap; depositing a contact etch stop layer over the gate dielectric cap and an interlayer dielectric (ILD) layer over the contact etch stop layer; performing a first etching process to form a gate contact opening extending through the ILD layer and terminating prior to reaching the etch-resistant layer; performing a second etching process to deepen the gate contact opening, wherein the second etching process etches the etch-resistant layer at a slower etch rate than etching the contact etch stop layer; and forming a gate contact in the deepened gate contact opening.

Abstract: Examples pertaining to re-transmission cyclic redundancy check (CRC) for polar coding incremental-redundancy hybrid automatic repeat request (IR-HARQ) are described. An apparatus (e.g., UE) encodes a plurality of information bits using a polar code to generate a polar code block (CB). The apparatus performs one or more transmissions of the polar CB using hybrid automatic repeat request (HARQ) by performing an initial transmission of the polar CB and performing a re-transmission of the polar CB with a re-transmission cyclic redundancy check (ReTX CRC).

Abstract: The present disclosure includes an ion implantation step that creates doped regions in gate dielectric caps. The doped regions have a different material composition and hence a different etch selectivity than un-doped regions in the gate dielectric caps. The doped regions thus allow for slowing down a subsequent etching process of forming gate contact openings.

Abstract: A method of providing tracking reference signal (TRS) in idle mode for power consumption enhancements is proposed. A user equipment (UE) operates in an idle mode of communication with a wireless communication network, and receives a system information block (SIB) or a paging early indication (PEI) from the wireless communication network when the UE is in the idle mode. The received SIB or PEI includes TRS configuration. The UE detects a TRS from the wireless communication network based on the TRS configuration when the UE is in the idle mode.

Abstract: A rotary positioning device includes a base, a fixing seat assembled on the shaft and stopper of the base and having and a movable positioning body respectively placed in each horizontal through-hole thereof, a rotation unit including a driving member and a rotating member and assembled outside the fixing seat, the driving member including a rotating shaft movably installed inside the protruding shaft portion of the fixing seat and a connecting portion located on one side of the rotating shaft, the rotating member including two inner shoulders that rotate and resist or retreat from the clamping portion of the fixing seat and two pushing portions for pressing the respective movable positioning bodies for lateral displacement in each through-hole, and an elastic member placed between the protruding shaft portion of the fixing seat and the rotating shaft of the driving member.

Abstract: A method of supporting active bandwidth part (BWP) switching under carrier aggregation (CA) is proposed. To avoid longer switching delay and multiple interruptions in other component carriers (CCs)/cells, the starting time of the later active BWP switching in one cell should fall outside the switching delay of the earlier active BWP switching in another cell. If the later active BWP switching is DCI-based, then the network should schedule the later active BWP switching outside the switching delay of the earlier active BWP switching. If the later active BWP switching is timer-based, then the UE should not perform the later active BWP switching until the earlier active BWP switching is completed.

Abstract: A method comprises forming a gate structure over a semiconductor substrate; forming an etch stop layer over the gate structure and an ILD layer over the etch stop layer; performing a first etching process to form a gate contact opening extending through the ILD layer into the etch stop layer, resulting in a sidewall of the etch stop layer being exposed in the gate contact opening; oxidizing the exposed sidewall of the etch stop layer; after oxidizing the exposed sidewall of the etch stop layer, performing a second etching process to deepen the gate contact opening; and forming a gate contact in the deepened gate contact opening.

Abstract: A method of UE power profile adaptation to traffic and UE power consumption characteristics based on power profile is proposed. In one preferred embodiment, hybrid of bandwidth part (BWP) and power profile is proposed. UE is configured with multiple BWPs and each BWP includes a set of power profiles. Two types of adaptation triggering can be used, a first type of trigger is based on power saving signals sent from the network, and the second type of trigger is based on timers. When the traffic characteristic for UE changes, the network can send a power saving signal to UE to trigger power profile adaptation, e.g., BWP+power profile switching. When traffic has been digested and becomes sporadic, then power profile adaptation can be triggered based on timers, e.g., a timer for BWP adaptation and another timer for power profile adaptation.

Abstract: A light-emitting semiconductor substrate, which is applied to a light-emitting semiconductor structure, includes a base and a plurality of particle groups. The base includes an upper surface. The particle groups are on the upper surface or inside the base dispersedly, and each of the particle groups includes Sn, Sn compounds or combinations thereof.

Abstract: Various solutions for enhancements on paging early indication (PEI) design are described. An apparatus may receive a PEI from a network node of a wireless network. The PEI is included in a downlink control information (DCI) with a cyclic redundancy check (CRC) scrambled by a paging early indication-radio network temporary identifier (PEI-RNTI). The apparatus may monitor a paging occasion (PO) associated with the apparatus in a case that the PEI indicates there being a paging for a subgroup to which the apparatus belongs.

Abstract: A method of introducing a Downlink Control Information (DCI)-based early paging indication (PEI) for power consumption enhancements in a 5G/NR network is proposed. In particular, a Base Station (BS) can transmit a message including a PEI to a User Equipment (UE) when the UE is under an idle ode. Then, the UE can receive the PEI under the idle mode and determine whether to monitor a Paging Occasion (PO) according to the PEI. In some embodiments, a format of the message including the PEI can include a format of DCI.