Abstract: A memory controller such as for use with a synchronous dynamic random access memory (SDRAM) wherein an active row at the end of each transfer can either be left active or closed by precharging the row. The memory controller uses a history register to keep track of the results of a number of prior accesses to each memory bank, remembering whether the access was to the same row as an immediately prior access. For each new memory access, the memory controller either asserts or deasserts a precharge enable signal depending on the state of the history bits. As a result, the memory controller is more likely to have a correct row open on a subsequent access, and less likely to have a wrong row open.