Patents by Inventor Dean J. Burdick

Dean J. Burdick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10540206
    Abstract: A method, program product, and system is provided for dynamic virtual processor management in a computer having a plurality of concurrent multi-threaded physical processors. An active logical partition is assigned to one of a plurality of shared processor pools, each shared processor pool having a virtual processor manager mode. A target performance metric for a workload in the active logical partition is compared to a calculated CPU utilization ratio or a calculated response time ratio. The workload in the active logical partition is dynamically moved from the assigned shared processor pool to a logical partition in another of the plurality of shared processor pools based on the target performance metric not being met in the active logical partition, and wherein the logical partition in another of the plurality of shared processor pools is configured to meet the target performance metric.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Dean J. Burdick, Bruce Mealey, Bret R. Olszewski, Basu Vaidyanathan
  • Publication number: 20180246761
    Abstract: A method, program product, and system is provided for dynamic virtual processor management in a computer having a plurality of concurrent multi-threaded physical processors. An active logical partition is assigned to one of a plurality of shared processor pools, each shared processor pool having a virtual processor manager mode. A target performance metric for a workload in the active logical partition is compared to a calculated CPU utilization ratio or a calculated response time ratio. The workload in the active logical partition is dynamically moved from the assigned shared processor pool to a logical partition in another of the plurality of shared processor pools based on the target performance metric not being met in the active logical partition, and wherein the logical partition in another of the plurality of shared processor pools is configured to meet the target performance metric.
    Type: Application
    Filed: May 2, 2018
    Publication date: August 30, 2018
    Inventors: Dean J. Burdick, Bruce Mealey, Bret R. Olszewski, Basu Vaidyanathan
  • Patent number: 9996393
    Abstract: A method, program product, and system is provided for dynamic virtual processor management in a computer having a plurality of concurrent multi-threaded physical processors. A workload is assigned to a first virtual processor manager pool based on a virtual processor manager mode of the first virtual processor manager pool. A current utilization ratio and a response time ratio for the workload are calculated. The workload is dynamically moved to a second virtual processor manager pool based on either the current utilization ratio or the response time ratio exceeding a configurable threshold. The workload is dynamically moved between virtual processor manager pools to realize target performance metric requirements.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Dean J. Burdick, Bruce Mealey, Bret R. Olszewski, Basu Vaidyanathan
  • Patent number: 9733965
    Abstract: Mechanisms are provided for dynamically adjusting assignment of software threads to hardware threads in virtual machine (VM) environments. The mechanisms receive, by a virtual machine manager (VMM), an indication of workload priority from a plurality of VMs. The indication indicates a priority of a workload executing on each VM in the plurality of VMs. The mechanisms provide, by the VMM, an indication of physical resource usage to each VM. The indication of physical resource usage is an indication of physical resource usage across all VMs in the plurality of VMs. The mechanisms automatically adjust, by each VM, assignment of corresponding software threads to hardware threads based on the indication of physical resource usage and a priority of a workload executing on the VM to achieve a balance of usage of hardware threads across all VMs in the plurality of VMs.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: August 15, 2017
    Assignee: International Business Machines Corporation
    Inventors: Vaijayanthimala K. Anand, Dean J. Burdick, Bruce G. Mealey, Dirk Michel
  • Patent number: 9727361
    Abstract: Mechanisms are provided for dynamically adjusting assignment of software threads to hardware threads in virtual machine (VM) environments. The mechanisms receive, by a virtual machine manager (VMM), an indication of workload priority from a plurality of VMs. The indication indicates a priority of a workload executing on each VM in the plurality of VMs. The mechanisms provide, by the VMM, an indication of physical resource usage to each VM. The indication of physical resource usage is an indication of physical resource usage across all VMs in the plurality of VMs. The mechanisms automatically adjust, by each VM, assignment of corresponding software threads to hardware threads based on the indication of physical resource usage and a priority of a workload executing on the VM to achieve a balance of usage of hardware threads across all VMs in the plurality of VMs.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: August 8, 2017
    Assignee: International Business Machines Corporation
    Inventors: Vaijayanthimala K. Anand, Dean J. Burdick, Bruce G. Mealey, Dirk Michel
  • Publication number: 20170147410
    Abstract: A method, program product, and system is provided for dynamic virtual processor management in a computer having a plurality of concurrent multi-threaded physical processors. A workload is assigned to a first virtual processor manager pool based on a virtual processor manager mode of the first virtual processor manager pool. A current utilization ratio and a response time ratio for the workload are calculated. The workload is dynamically moved to a second virtual processor manager pool based on either the current utilization ratio or the response time ratio exceeding a configurable threshold. The workload is dynamically moved between virtual processor manager pools to realize target performance metric requirements.
    Type: Application
    Filed: November 19, 2015
    Publication date: May 25, 2017
    Inventors: Dean J. Burdick, Bruce Mealey, Bret R. Olszewski, Basu Vaidyanathan
  • Patent number: 9417905
    Abstract: Terminating an accelerator application program in a hybrid computing environment that includes a host computer having a host computer architecture and an accelerator having an accelerator architecture, where the host computer and the accelerator are adapted to one another for data communications by a system level message passing module (‘SLMPM’), and terminating an accelerator application program in a hybrid computing environment includes receiving, by the SLMPM from a host application executing on the host computer, a request to terminate an accelerator application program executing on the accelerator; terminating, by the SLMPM, execution of the accelerator application program; returning, by the SLMPM to the host application, a signal indicating that execution of the accelerator application program was terminated; and performing, by the SLMPM, a cleanup of the execution environment associated with the terminated accelerator application program.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: August 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Archer, Gregory H. Bellows, Dean J. Burdick, James E. Carey, Jeffrey M. Ceason, Matthew W. Markland, Philip J. Sanders, Gordon G. Stewart
  • Publication number: 20150169347
    Abstract: Mechanisms are provided for dynamically adjusting assignment of software threads to hardware threads in virtual machine (VM) environments. The mechanisms receive, by a virtual machine manager (VMM), an indication of workload priority from a plurality of VMs. The indication indicates a priority of a workload executing on each VM in the plurality of VMs. The mechanisms provide, by the VMM, an indication of physical resource usage to each VM. The indication of physical resource usage is an indication of physical resource usage across all VMs in the plurality of VMs. The mechanisms automatically adjust, by each VM, assignment of corresponding software threads to hardware threads based on the indication of physical resource usage and a priority of a workload executing on the VM to achieve a balance of usage of hardware threads across all VMs in the plurality of VMs.
    Type: Application
    Filed: December 12, 2013
    Publication date: June 18, 2015
    Applicant: International Business Machines Corporation
    Inventors: Vaijayanthimala K. Anand, Dean J. Burdick, Bruce G. Mealey, Dirk Michel
  • Publication number: 20150169350
    Abstract: Mechanisms are provided for dynamically adjusting assignment of software threads to hardware threads in virtual machine (VM) environments. The mechanisms receive, by a virtual machine manager (VMM), an indication of workload priority from a plurality of VMs. The indication indicates a priority of a workload executing on each VM in the plurality of VMs. The mechanisms provide, by the VMM, an indication of physical resource usage to each VM. The indication of physical resource usage is an indication of physical resource usage across all VMs in the plurality of VMs. The mechanisms automatically adjust, by each VM, assignment of corresponding software threads to hardware threads based on the indication of physical resource usage and a priority of a workload executing on the VM to achieve a balance of usage of hardware threads across all VMs in the plurality of VMs.
    Type: Application
    Filed: June 16, 2014
    Publication date: June 18, 2015
    Inventors: Vaijayanthimala K. Anand, Dean J. Burdick, Bruce G. Mealey, Dirk Michel
  • Patent number: 8266337
    Abstract: A method, system and program are provided for dynamically allocating DMA channel identifiers by virtualizing DMA transfer requests into available DMA channel identifiers using a channel bitmap listing of available DMA channels to select and set an allocated DMA channel identifier. Once an input value associated with the DMA transfer request is mapped to the selected DMA channel identifier, the DMA transfer is performed using the selected DMA channel identifier, which is then deallocated in the channel bitmap upon completion of the DMA transfer. When there is a request to wait for completion of the data transfer, the same input value is used with the mapping to wait on the appropriate logical channel. With this method, all available logical channels can be utilized with reduced instances of false-sharing.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: September 11, 2012
    Assignee: International Business Machines Corporation
    Inventors: Joaquin Madruga, Dean J. Burdick
  • Patent number: 8205207
    Abstract: A method, system and program are disclosed for automatically adjusting the allocation of a plurality of information processing system (IPS) resources among a plurality of logical partitions (LPARs). An LPAR is created on a first central processor complex (CPC) and a first LPAR identifier is generated. A configuration change manager is implemented on the LPAR to communicate changes in the LPAR's identifier to an automated resource manager (ARM). IPS resources are automatically allocated to the LPAR. If the LPAR is migrated a second CPC, a second LPAR identifier is similarly generated, resulting in an LPAR configuration change event. The ARM is notified that the migrated LPAR's identifier has changed and receives the changed LPAR identifier. Comparison operations are performed to determine whether the second LPAR identifier matches the first CPC. If not, resources allocated to the migrated LPAR are released for automated allocation to other LPARs comprising the first CPC.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: June 19, 2012
    Assignee: International Business Machines Corporation
    Inventors: Marcos A. Villarreal, Dean J. Burdick
  • Patent number: 8156498
    Abstract: A mechanism is provided for biasing placement of a software thread on a currently idle and dispatched processor. The operating system starts with the last logical processor on which the software thread ran and determines whether that processor is idle and dispatched and considers each logical processor until a currently dispatched and idle logical processor is found. If a currently dispatched and idle logical processor is not found, then the operating system biases placing the software thread on an idle logical processor.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: April 10, 2012
    Assignee: International Business Machines Corporation
    Inventors: Vaijayanthimala K. Anand, Dean J. Burdick, Bret R. Olszewski
  • Patent number: 8108866
    Abstract: A mechanism is provided for determining whether to use cache affinity as a criterion for software thread dispatching in a shared processor logical partitioning data processing system. The server firmware may store data about when and/or how often logical processors are dispatched. Given these data, the operating system may collect metrics. Using the logical processor metrics, the operating system may determine whether cache affinity is likely to provide a significant performance benefit relative to the cost of dispatching a particular logical processor to the operating system.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: January 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Vaijayanthimala K. Anand, Dean J. Burdick, Bret R. Olszewski
  • Publication number: 20110191785
    Abstract: Terminating an accelerator application program in a hybrid computing environment that includes a host computer having a host computer architecture and an accelerator having an accelerator architecture, where the host computer and the accelerator are adapted to one another for data communications by a system level message passing module (‘SLMPM’), and terminating an accelerator application program in a hybrid computing environment includes receiving, by the SLMPM from a host application executing on the host computer, a request to terminate an accelerator application program executing on the accelerator; terminating, by the SLMPM, execution of the accelerator application program; returning, by the SLMPM to the host application, a signal indicating that execution of the accelerator application program was terminated; and performing, by the SLMPM, a cleanup of the execution environment associated with the terminated accelerator application program.
    Type: Application
    Filed: February 3, 2010
    Publication date: August 4, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles J. Archer, Gregory H. Bellows, Dean J. Burdick, James E. Carey, Jeffrey M. Ceason, Matthew W. Markland, Philip J. Sanders, Gordon G. Stewart
  • Patent number: 7870551
    Abstract: A mechanism is provided for biasing placement of a software thread on a currently idle and dispatched processor. The operating system starts with the last logical processor on which the software thread ran and determines whether that processor is idle and dispatched and considers each logical processor until a currently dispatched and idle logical processor is found. If a currently dispatched and idle logical processor is not found, then the operating system biases placing the software thread on an idle logical processor.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: January 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Vaijayanthimala K. Anand, Dean J. Burdick, Bret R. Olszewski
  • Patent number: 7865631
    Abstract: A method, system and program are provided for dynamically allocating DMA channel identifiers to multiple DMA transfer requests that are grouped in time by virtualizing DMA transfer requests into an available DMA channel identifier using a channel bitmap listing of available DMA channels to select and set an allocated DMA channel identifier. Once the input values associated with the DMA transfer requests are mapped to the selected DMA channel identifier, the DMA transfers are performed using the selected DMA channel identifier, which is then deallocated in the channel bitmap upon completion of the DMA transfers. When there is a request to wait for completion of the data transfers, the same input values are used with the mapping to wait on the appropriate logical channel. With this method, all available logical channels can be utilized with reduced instances of false-sharing.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: January 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Joaquin Madruga, Dean J. Burdick
  • Patent number: 7865895
    Abstract: A mechanism is provided for determining whether to use cache affinity as a criterion for software thread dispatching in a shared processor logical partitioning data processing system. The server firmware may store data about when and/or how often logical processors are dispatched. Given these data, the operating system may collect metrics. Using the logical processor metrics, the operating system may determine whether cache affinity is likely to provide a significant performance benefit relative to the cost of dispatching a particular logical processor to the operating system.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: January 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Vaijayanthimala K. Anand, Dean J. Burdick, Bret R. Olszewski
  • Publication number: 20090327613
    Abstract: A method for implementing a software-managed cache comprises determining an object identifier (ID) for each of a first set of objects of a plurality of objects resident in a local memory, to generate a first cache table, the first cache table comprising a plurality of entries. Each object comprises an object ID and an effective address. The method receives a request for an object, the request comprising an object ID. The method compares the received object ID with the entries in the first cache table. In the event the received object ID matches an entry in the first cache table, the method returns the matching entry in response to the request. In the event the received object ID does not match an entry in the first cache table, the method calculates an effective address in the local memory of the object associated with the object ID.
    Type: Application
    Filed: June 25, 2008
    Publication date: December 31, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark R. Nutter, Dean J. Burdick, Barry L. Minor
  • Publication number: 20090235270
    Abstract: A mechanism is provided for biasing placement of a software thread on a currently idle and dispatched processor. The operating system starts with the last logical processor on which the software thread ran and determines whether that processor is idle and dispatched and considers each logical processor until a currently dispatched and idle logical processor is found. If a currently dispatched and idle logical processor is not found, then the operating system biases placing the software thread on an idle logical processor.
    Type: Application
    Filed: May 30, 2008
    Publication date: September 17, 2009
    Applicant: International Business Machines Corporation
    Inventors: Vaijayanthimala K. Anand, Dean J. Burdick, Bret R. Olszewski
  • Publication number: 20090150575
    Abstract: A method, system and program are provided for dynamically allocating DMA channel identifiers to multiple DMA transfer requests that are grouped in time by virtualizing DMA transfer requests into an available DMA channel identifier using a channel bitmap listing of available DMA channels to select and set an allocated DMA channel identifier. Once the input values associated with the DMA transfer requests are mapped to the selected DMA channel identifier, the DMA transfers are performed using the selected DMA channel identifier, which is then deallocated in the channel bitmap upon completion of the DMA transfers. When there is a request to wait for completion of the data transfers, the same input values are used with the mapping to wait on the appropriate logical channel. With this method, all available logical channels can be utilized with reduced instances of false-sharing.
    Type: Application
    Filed: December 6, 2007
    Publication date: June 11, 2009
    Inventors: Joaquin Madruga, Dean J. Burdick