Patents by Inventor Dean Nobunaga
Dean Nobunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9443600Abstract: A method and apparatus that controls a peak-current condition in a multi-die memory, such as a solid-state drive, by determining by at least one die of the multi-die memory whether a subsequent memory operation is a high-current memory operation, such as an operation to enable a charge pump of the die, an operation to charge a bit line of the die, or a program/erase loop operation, or a combination thereof. The die enters a suspended-operation mode if the subsequent memory operation is determined to be a high current memory operation. Operation is resumed by the die in response to a resume operation event, such as, but not limited to, a command specifically address to the die, an indication from another die that a high-current memory operation is complete. Once operation is resumed, the die performs the high-current memory operation.Type: GrantFiled: March 28, 2013Date of Patent: September 13, 2016Assignee: Intel CorporationInventors: Ali Ghalam, Dean Nobunaga, Jason Guo
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Patent number: 9390049Abstract: Described embodiments include logical units within a memory device with control circuitry configured to assign a logical unit address to the logical unit. Apparatus including a plurality of the logical units arranged in a daisy chain configuration and methods of assigning logical unit addresses to the logical units are also disclosed.Type: GrantFiled: June 3, 2011Date of Patent: July 12, 2016Assignee: Micron Technology, Inc.Inventors: June Lee, Terry M. Grunzke, Dean Nobunaga
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Publication number: 20140293704Abstract: A method and apparatus that controls a peak-current condition in a multi-die memory, such as a solid-state drive, by determining by at least one die of the multi-die memory whether a subsequent memory operation is a high-current memory operation, such as an operation to enable a charge pump of the die, an operation to charge a bit line of the die, or a program/erase loop operation, or a combination thereof. The die enters a suspended-operation mode if the subsequent memory operation is determined to be a high current memory operation. Operation is resumed by the die in response to a resume operation event, such as, but not limited to, a command specifically address to the die, an indication from another die that a high-current memory operation is complete. Once operation is resumed, the die performs the high-current memory operation.Type: ApplicationFiled: March 28, 2013Publication date: October 2, 2014Inventors: Ali Ghalam, Dean Nobunaga, Jason Guo
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Patent number: 8806155Abstract: Memory devices and methods facilitate handling of data received by a memory device through the use of data grouping and assignment of data validity status values to grouped data. For example, data is received and delineated into one or more data groups and a data validity status is associated with each data group. Data groups having a valid status are latched into one or more cache registers for storage in an array of memory cells wherein data groups comprising an invalid status are rejected by the one or more cache registers.Type: GrantFiled: February 25, 2013Date of Patent: August 12, 2014Assignee: Micron Technology, Inc.Inventors: Luyen Vu, Uday Chandrasekhar, Dean Nobunaga
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Publication number: 20140068186Abstract: Memory devices and methods facilitate handling of data received by a memory device through the use of data grouping and assignment of data validity status values to grouped data. For example, data is received and delineated into one or more data groups and a data validity status is associated with each data group. Data groups having a valid status are latched into one or more cache registers for storage in an array of memory cells wherein data groups comprising an invalid status are rejected by the one or more cache registers.Type: ApplicationFiled: February 25, 2013Publication date: March 6, 2014Inventors: Luyen Vu, Uday Chandrasekhar, Dean Nobunaga
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Patent number: 8601331Abstract: A non-volatile memory device includes a block remapping system that offsets an input block address by the addresses of non-functional blocks to provide an output block address that is used to address the memory device. The system generates the output block addresses by, in effect, adding to the input block address the addresses of all non-functional blocks of memory that are between an initial address and the output block address. The system performs this function be comparing the input block address to the address of any defective block. If the address of the defective block is less than or equal to the input block address, the addresses of all defective blocks starting at the block address are added to the input block address. The system then iteratively performs this process using each output block address generated by the system in place of the input block address.Type: GrantFiled: May 20, 2011Date of Patent: December 3, 2013Assignee: Micron Technology, Inc.Inventors: Dean Nobunaga, Hanqing Li
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Patent number: 8462536Abstract: The present description relates to non-volatile memory arrays and the operation thereof In at least one embodiment, the non-volatile memory array may include a plurality of memory modules coupled in a daisy chain with enable in/out signals, and a single chip enable signal coupled in parallel to each memory module. With such a configuration, all memory units within each of the memory modules of each memory array may be addressed with the single chip enable signal.Type: GrantFiled: March 11, 2011Date of Patent: June 11, 2013Assignee: Intel CorporationInventors: Dean Nobunaga, Terry Grunzke, Ali Ghalam
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Patent number: 8416628Abstract: Methods for sensing, memory devices, and memory systems are disclosed. In one such memory device, a local sense circuit provides sensing of an upper group of memory cells while a global sense circuit provides sensing of a lower group of memory cells. Data sensed by the local sense circuit is transferred to the global sense circuit over local data lines or a global transfer line that is multiplexed to the local data lines. An alternate embodiment uses the local sense circuit to sense both upper and lower groups of memory cells.Type: GrantFiled: September 11, 2012Date of Patent: April 9, 2013Assignee: Micron Technology, Inc.Inventors: Dean Nobunaga, William Kammerer, Uday Chandrasekhar
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Patent number: 8386724Abstract: Memory devices and methods facilitate handling of data received by a memory device through the use of data grouping and assignment of data validity status values to grouped data. For example, data is received and delineated into one or more data groups and a data validity status is associated with each data group. Data groups having a valid status are latched into one or more cache registers for storage in an array of memory cells wherein data groups comprising an invalid status are rejected by the one or more cache registers.Type: GrantFiled: February 19, 2009Date of Patent: February 26, 2013Assignee: Micron Technology, Inc.Inventors: Luyen Vu, Uday Chandrasekhar, Dean Nobunaga
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Publication number: 20130003465Abstract: Methods for sensing, memory devices, and memory systems are disclosed. In one such memory device, a local sense circuit provides sensing of an upper group of memory cells while a global sense circuit provides sensing of a lower group of memory cells. Data sensed by the local sense circuit is transferred to the global sense circuit over local data lines or a global transfer line that is multiplexed to the local data lines. An alternate embodiment uses the local sense circuit to sense both upper and lower groups of memory cells.Type: ApplicationFiled: September 11, 2012Publication date: January 3, 2013Inventors: Dean Nobunaga, William Kammerer, Uday Chandrasekhar
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Publication number: 20120311297Abstract: Described embodiments include logical units within a memory device with control circuitry configured to assign a logical unit address to the logical unit. Apparatus including a plurality of the logical units arranged in a daisy chain configuration and methods of assigning logical unit addresses to the logical units are also disclosed.Type: ApplicationFiled: June 3, 2011Publication date: December 6, 2012Inventors: June Lee, Terry M. Grunzke, Dean Nobunaga
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Patent number: 8321713Abstract: A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the register has bits to indicate the desired mode and the input clock frequency. In the fast data access mode, a clock delay circuit uses the clock frequency setting bits to select a delay to be added to the input clock. The higher the clock frequency, the less the added delay. The delayed clock generates FIFO control signals to control a data FIFO register. During the fast data access mode, the data is output from the data FIFO register at a faster rate than in the standard clock mode.Type: GrantFiled: November 3, 2009Date of Patent: November 27, 2012Assignee: Micron Technology, Inc.Inventor: Dean Nobunaga
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Patent number: 8295098Abstract: Methods for sensing, memory devices, and memory systems are disclosed. In one such memory device, a local sense circuit provides sensing of an upper group of memory cells while a global sense circuit provides sensing of a lower group of memory cells. Data sensed by the local sense circuit is transferred to the global sense circuit over local data lines or a global transfer line that is multiplexed to the local data lines. An alternate embodiment uses the local sense circuit to sense both upper and lower groups of memory cells.Type: GrantFiled: June 16, 2010Date of Patent: October 23, 2012Assignee: Micron Technology, Inc.Inventors: Dean Nobunaga, William Kammerer, Uday Chandrasekhar
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Publication number: 20120230110Abstract: The present description relates to non-volatile memory arrays and the operation thereof In at least one embodiment, the non-volatile memory array may include a plurality of memory modules coupled in a daisy chain with enable in/out signals, and a single chip enable signal coupled in parallel to each memory module.Type: ApplicationFiled: March 11, 2011Publication date: September 13, 2012Inventors: Dean Nobunaga, Terry Grunzke, Ali Ghalam
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Publication number: 20110310675Abstract: Methods for sensing, memory devices, and memory systems are disclosed. In one such memory device, a local sense circuit provides sensing of an upper group of memory cells while a global sense circuit provides sensing of a lower group of memory cells. Data sensed by the local sense circuit is transferred to the global sense circuit over local data lines or a global transfer line that is multiplexed to the local data lines. An alternate embodiment uses the local sense circuit to sense both upper and lower groups of memory cells.Type: ApplicationFiled: June 16, 2010Publication date: December 22, 2011Inventors: Dean Nobunaga, William Kammerer, Uday Chandrasekhar
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Publication number: 20110219260Abstract: A non-volatile memory device includes a block remapping system that offsets an input block address by the addresses of non-functional blocks to provide an output block address that is used to address the memory device. The system generates the output block addresses by, in effect, adding to the input block address the addresses of all non-functional blocks of memory that are between an initial address and the output block address. The system performs this function be comparing the input block address to the address of any defective block. If the address of the defective block is less than or equal to the input block address, the addresses of all defective blocks starting at the block address are added to the input block address. The system then iteratively performs this process using each output block address generated by the system in place of the input block address.Type: ApplicationFiled: May 20, 2011Publication date: September 8, 2011Applicant: Micron Technology, Inc.Inventors: DEAN NOBUNAGA, Hanqing Li
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Patent number: 7958439Abstract: A non-volatile memory device includes a block remapping system that offsets an input block address by the addresses of non-functional blocks to provide an output block address that is used to address the memory device. The system generates the output block addresses by, in effect, adding to the input block address the addresses of all non-functional blocks of memory that are between an initial address and the output block address. The system performs this function be comparing the input block address to the address of any defective block. If the address of the defective block is less than or equal to the input block address, the addresses of all defective blocks starting at the block address are added to the input block address. The system then iteratively performs this process using each output block address generated by the system in place of the input block address.Type: GrantFiled: May 26, 2010Date of Patent: June 7, 2011Assignee: Micron Technology, Inc.Inventors: Dean Nobunaga, Hanqing Li
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Patent number: 7889562Abstract: Memory devices and methods of operating memory devices are provided. In one such embodiment, a programming voltage pulse or an erase voltage pulse is applied to memory cells of a memory device. A rate at which programming or erasing is proceeding is determined. The programming voltage pulse or the erase voltage pulse is adjusted at least partially in response to the determined rate. The adjusted programming voltage pulse or the adjusted erase voltage pulse is applied to the memory cells that failed to program or erase.Type: GrantFiled: November 9, 2009Date of Patent: February 15, 2011Assignee: Micron Technology, Inc.Inventor: Dean Nobunaga
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Publication number: 20100235679Abstract: A non-volatile memory device includes a block remapping system that offsets an input block address by the addresses of non-functional blocks to provide an output block address that is used to address the memory device. The system generates the output block addresses by, in effect, adding to the input block address the addresses of all non-functional blocks of memory that are between an initial address and the output block address. The system performs this function be comparing the input block address to the address of any defective block. If the address of the defective block is less than or equal to the input block address, the addresses of all defective blocks starting at the block address are added to the input block address. The system then iteratively performs this process using each output block address generated by the system in place of the input block address.Type: ApplicationFiled: May 26, 2010Publication date: September 16, 2010Applicant: Micron Technology, Inc.Inventors: DEAN NOBUNAGA, Hanqing Li
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Publication number: 20100211733Abstract: Memory devices and methods facilitate handling of data received by a memory device through the use of data grouping and assignment of data validity status values to grouped data. For example, data is received and delineated into one or more data groups and a data validity status is associated with each data group. Data groups having a valid status are latched into one or more cache registers for storage in an array of memory cells wherein data groups comprising an invalid status are rejected by the one or more cache registers.Type: ApplicationFiled: February 19, 2009Publication date: August 19, 2010Inventors: Luyen Vu, Uday Chandrasekhar, Dean Nobunaga