Abstract: A method and apparatus for determining integrated circuit layouts of a random access memory (RAM) from a virtual circuit description and specification of a process technology. Starting with high-level descriptions of a circuit, a virtual geometric description of the circuit is developed in terms of reference points relative to a substrate surface. When the process technology is specified, the relationships among the reference points is determined, as in the layout of the RAM. These relationships account for variable sizing of circuit features and pitch matching of circuit features. A connectivity model and a simulation model of the RAM are also produced by the method and apparatus. These model can be used to verify that the RAM is connected as desired and has the desired performance.