Abstract: A system includes a server associated with a resource utilization, a database storing historical data including resource utilization values over a first time period, and a processor. The processor identifies, from the historical data, a maximum resource utilization value and determines a duration of time for which the resource utilization exceeds a percentage of the maximum. The processor predicts, based on the historical data, a maximum predicted resource utilization value over a second time period, later than the first. The processor also determines, based on the historical data, an upper bound of a resource utilization confidence interval. The processor generates, based on the maximum value over the first time period, the duration of time, the maximum predicted value over the second time period, and the upper bound, a recommendation to consolidate the server with a second server and/or to release computational resources. The processor transmits the recommendation to an administrator.

Abstract: A system includes a server associated with a resource utilization, a database storing historical data including resource utilization values over a first time period, and a processor. The processor identifies, from the historical data, a maximum resource utilization value and determines a duration of time for which the resource utilization exceeds a percentage of the maximum. The processor predicts, based on the historical data, a maximum predicted resource utilization value over a second time period, later than the first. The processor also determines, based on the historical data, an upper bound of a resource utilization confidence interval. The processor generates, based on the maximum value over the first time period, the duration of time, the maximum predicted value over the second time period, and the upper bound, a recommendation to consolidate the server with a second server and/or to release computational resources. The processor transmits the recommendation to an administrator.

Abstract: A system, method, and device are disclosed. In one embodiment, the device comprises logic to determine whether a received transaction layer packet (TLP) has a compressed header and, if the received TLP has a compressed header, logic to decompress the header.

Abstract: A method, device, and system are disclosed. In one embodiment, the method comprises transitioning one or more lanes of a multi-lane serial link from a fully operational power state to a low power state and keeping one or more other lanes of the multi-lane serial link in the fully operational power state to allow one or more data transfers across the remaining operational lanes in the link.

Abstract: A method and apparatus for meeting compliance for debugging and testing a multi-speed, point-to-point link. In one embodiment, the method includes the selection of a compliance speed for a point-to-point link from at least two link frequencies supported by the point-to-point link. Once the compliance speed is selected for the point-to-point link, the point-to-point link is caused to enter a compliance testing mode. During compliance testing mode, a controller of the point-to-point link sets a compliance speed of the point-to-point link to the selected compliance speed. Once a compliance speed is set, a transmitter of the point-to-point link transmits a compliance pattern at the selected compliance speed. In one embodiment, the transmission of the compliance pattern at the selected compliance speed is used to generate a worst case eye diagram to determine compliance of the point-to-point link to a link specification. Other embodiments are described and claimed.

Abstract: A method and an apparatus to track address translation in I/O virtualization have been presented. In one embodiment, the method includes initiating a page walk if none of a plurality of entries in a translation lookaside buffer (TLB) in a direct memory access (DMA) remap engine matches a guest physical address of an incoming address translation request. The method further includes performing the page walk in parallel with one or more ongoing page walks and tracking progress of the page walk using one or more of a plurality of flags and state information pertaining to intermediate states of the page walk stored in the TLB. Other embodiments have been claimed and described.

Abstract: Point-to-point links between devices are brought up at a slowest available speed, and a faster link speed is negotiated after reaching an operational state.

Abstract: A method, device, and system are disclosed. In one embodiment, the method comprises discovering a failure on a PCI Express interconnect, determining whether a failure override bit has been set to override the standard PCI Express Polling.Compliance state for the failure on the PCI Express interconnect, and if the failure override bit has been set, entering PCI Express Polling.Configuration state if any one lane of the interconnect successfully completes the transmitting and receiving training sequence requirements in PCI Express Polling.Active state.

Abstract: A device includes a first memory that includes a page in progress field. A read processing engine is connected to the first memory. The read processing engine to interleave read requests based on the page in progress field.

Abstract: Various embodiments of the invention relate to an apparatus and method for efficiently implementing out-of-order servicing of read requests originating from an input/output (I/O) interface with minimal additional storage. For example, a number of read entries may be generated from data read requests stored in a first-in-first-out in a first order. The read entries are stored in a storage device and each read entry identifies internal data reads to read data to service the data read request to which the read entry corresponds. A controller coupled to the storage structure may then submit the internal data reads a central arbiter to read data in a second order that is different than the first order. Moreover, the controller also allows the second order to include internal data reads from one read entry, before a completing servicing of another partially serviced read entry, thus providing “simultaneous” servicing of several read entries.

Abstract: Various embodiments of the invention provide a frequency shifter to vary the frequency of data transmitted over time, such as to increase and decrease the frequency of test data transmitted over time to verify a digital communication device's ability to receive data having various frequencies within a specific parameter range. The frequency shifter includes a frequency modifier to shift or vary an input clock frequency to a variety of output clock frequencies, such as according to a test protocol. The frequency shifter also includes an elastic data buffer to receive the test data at the input clock frequency and to output the test data at the plurality of output clock frequencies provided by the frequency modifier.