Abstract: A method of fabricating a glassy carbon film is described. The method includes forming a soluble layer on a substrate, forming a lift-off stack that includes a lift-off mask layer and a hard-mask layer, and forming a pattern in the lift-off stack to expose a portion of the soluble layer. The exposed portions of the soluble layer are removed to expose a portion of the substrate. A carbon material is over the exposed portion of the substrate. The soluble layer is dissolved in a solvent, and the lift-off stack is lifted-off.

Abstract: The present invention relates to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.

Abstract: A method of fabricating a glassy carbon film is described. The method includes forming a soluble layer on a substrate, forming a lift-off stack that includes a lift-off mask layer and a hard-mask layer, and forming a pattern in the lift-off stack to expose a portion of the soluble layer. The exposed portions of the soluble layer are removed to expose a portion of the substrate. A carbon material is over the exposed portion of the substrate. The soluble layer is dissolved in a solvent, and the lift-off stack is lifted-off.

Abstract: Integrated circuits including at least two electrically conductive interconnect lines and methods of manufacturing generally include a surface of the integrated circuit. At least two electrically conductive interconnect lines are separated by a space of less than 90 nm and are formed on the surface. Each of the at least two interconnect lines includes a metal cap, a copper conductor having an average grain size greater than a line width of the interconnect. A liner layer is provided, wherein the liner layer and the metal cap encapsulate the copper conductor. A dielectric layer overlaying the at least two electrically conductive interconnect lines and extending along sidewalls thereof is provided, wherein the dielectric layer is configured to provide an airgap between the at least two interconnect lines at the spacing.

Abstract: Embodiments of the invention are directed to a biosensing integrated circuit (IC). A non-limiting example of the biosensing IC includes a plurality of semiconductor substrate layers. A sensor element is formed over a first one of the plurality of semiconductor substrate layers, wherein the sensor element is configured to, based at least in part on the sensor element interacting with a predetermined material, generate data representing a measurable electrical parameter. An adhesion enhancement region is configured to physically couple the sensor element to the first one of the plurality of semiconductor substrate layers. In some embodiments of the invention, the biosensing IC further includes an electrically conductive interconnect network configured to communicatively couple the data representing the measurable electrical parameter to computer elements.

Abstract: The present invention relates to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.

Abstract: Embodiments of the invention are directed to a biosensing integrated circuit (IC). A non-limiting example of the biosensing IC includes a plurality of semiconductor substrate layers. A sensor element is formed over a first one of the plurality of semiconductor substrate layers, wherein the sensor element is configured to, based at least in part on the sensor element interacting with a predetermined material, generate data representing a measureable electrical parameter. An adhesion enhancement region is configured to physically couple the sensor element to the first one of the plurality of semiconductor substrate layers. In some embodiments of the invention, the biosensing IC further includes an electrically conductive interconnect network configured to communicatively couple the data representing the measureable electrical parameter to computer elements.

Abstract: A conformal disposable absorber is disclosed which is capable of providing efficient heat transfer to an embedded memory device during a localized absorber anneal, without adversary impacting the back-end-of-the-line (BEOL) structure. The disposable absorber is composed of an amorphous carbonitride material that can be designed to have a low reflection coefficient for laser/flash illumination, and a high extinction coefficient for efficient laser/flash illumination absorption. The disposable absorber is formed at a temperature of 400° C. or less.

Abstract: A conformal disposable absorber is disclosed which is capable of providing efficient heat transfer to an embedded memory device during a localized absorber anneal, without adversary impacting the back-end-of-the-line (BEOL) structure. The disposable absorber is composed of an amorphous carbonitride material that can be designed to have a low reflection coefficient for laser/flash illumination, and a high extinction coefficient for efficient laser/flash illumination absorption. The disposable absorber is formed at a temperature of 400° C. or less.

Abstract: Embodiments of the invention are directed to a biosensing integrated circuit (IC). A non-limiting example of the biosensing IC includes a plurality of semiconductor substrate layers. A sensor element is formed over a first one of the plurality of semiconductor substrate layers, wherein the sensor element is configured to, based at hleast in part on the sensor element interacting with a predetermined material, generate data representing a measureable electrical parameter. An adhesion enhancement region is configured to physically couple the sensor element to the first one of the plurality of semiconductor substrate layers. In some embodiments of the invention, the biosensing IC further includes an electrically conductive interconnect network configured to communicatively couple the data representing the measureable electrical parameter to computer elements.

Abstract: Embodiments of the invention are directed to a biosensing integrated circuit (IC). A non-limiting example of the biosensing IC includes a plurality of semiconductor substrate layers. A sensor element is formed over a first one of the plurality of semiconductor substrate layers, wherein the sensor element is configured to, based at least in part on the sensor element interacting with a predetermined material, generate data representing a measurable electrical parameter. An adhesion enhancement region is configured to physically couple the sensor element to the first one of the plurality of semiconductor substrate layers. In some embodiments of the invention, the biosensing IC further includes an electrically conductive interconnect network configured to communicatively couple the data representing the measurable electrical parameter to computer elements.

Abstract: Techniques and structures for laser doping of crystalline semiconductors using a dopant-containing amorphous silicon stack for dopant source and passivation are provided. An example method includes forming a dopant-containing amorphous silicon layer stack on at least one portion of a surface of a crystalline semiconductor layer; and irradiating a selected area of the dopant-containing amorphous silicon layer stack, wherein the selected area of the dopant-containing amorphous silicon layer stack interacts with an upper portion of the underlying crystalline semiconductor layer to form a doped, conductive crystalline region, and each non-selected area of the dopant-containing amorphous silicon layer stack remains intact on the at least one portion of the surface of the crystalline semiconductor layer.

Abstract: Integrated circuits including at least two electrically conductive interconnect lines and methods of manufacturing generally include a surface of the integrated circuit. At least two electrically conductive interconnect lines are separated by a space of less than 90 nm and are formed on the surface. Each of the at least two interconnect lines includes a metal cap, a copper conductor having an average grain size greater than a line width of the interconnect. A liner layer is provided, wherein the liner layer and the metal cap encapsulate the copper conductor. A dielectric layer overlaying the at least two electrically conductive interconnect lines and extending along sidewalls thereof is provided, wherein the dielectric layer is configured to provide an airgap between the at least two interconnect lines at the spacing.

Abstract: A scaled dielectric stack interlayer, compatible with subsequent high temperature processing with good electrical transport & reliability properties is provided. A method for forming a conformal aSi:H passivation layer on a semiconductor device is described. A patterned semiconductor wafer is placed in in a process chamber with a first layer formed thereon and a second layer formed thereon, the first layer and the second layer being two different materials Next, a SixH(2x+2) based deposition up to a temperature of 400 degrees Celsius is used on the first layer and the second layer thereby forming a conformal aSi:H passivating layer is formed at a higher rate of deposition on the first layer selectively and a lower rate of deposit on the second layer.

Abstract: A material stack is formed on the surface of a semiconductor substrate. The top layer of the material stack comprises at least an organic planarization layer. A neutral hard mask layer is formed on the top of the organic planarization layer. The neutral hard mask layer is neutral to the block copolymers used for direct self-assembly. A plurality of template etch stacks are then formed on top of the neutral hard mask layer. After formation of the template etch stacks, neutrality recovery is performed on the neutral hard mask layer and the top portions of the template etch stacks, the vertical sidewalls of the template etch stacks being substantially unaffected by the neutrality recovery. A template for DSA is thus obtained.

Abstract: A substrate incorporating semiconductor regions electrically isolated by shallow trenches filled with hexagonal, textured or columnar boron nitride. A process for filling shallow trenches in a semiconductor substrate with columnar textured boron nitride using pulsed plasma enhanced chemical vapor deposition (Pulsed PECVD) and plasma assisted atomic layer deposition (PAALD).

Abstract: Embodiments are directed to an electromagnetic memory device having a memory cell and an encapsulation layer formed over the memory cell. The memory cell may include a magnetic tunnel junction (MTJ), and the encapsulation layer may be formed from a layer of hydrogenated amorphous silicon. Amorphous silicon improves the coercivity of the MTJ but by itself is conductive. Adding hydrogen to amorphous silicon passivates dangling bonds of the amorphous silicon, thereby reducing the ability of the resulting hydrogenated amorphous silicon layer to provide a parasitic current path to the MTJ. The hydrogenated amorphous silicon layer may be formed using a plasma-enhanced chemical vapor deposition, which can be tuned to enable a hydrogen level of approximately 10 to approximately 20 percent. By keeping subsequent processing operations at or below about 400 Celsius, the resulting layer of hydrogenated amorphous silicon can maintain its hydrogen level of approximately 10 to 20 percent.

Abstract: Embodiments are directed to an electromagnetic memory device having a memory cell and an encapsulation layer formed over the memory cell. The memory cell may include a magnetic tunnel junction (MTJ), and the encapsulation layer may be formed from a layer of hydrogenated amorphous silicon. Amorphous silicon improves the coercivity of the MTJ but by itself is conductive. Adding hydrogen to amorphous silicon passivates dangling bonds of the amorphous silicon, thereby reducing the ability of the resulting hydrogenated amorphous silicon layer to provide a parasitic current path to the MTJ. The hydrogenated amorphous silicon layer may be formed using a plasma-enhanced chemical vapor deposition, which can be tuned to enable a hydrogen level of approximately 10 to approximately 20 percent. By keeping subsequent processing operations at or below about 400 Celsius, the resulting layer of hydrogenated amorphous silicon can maintain its hydrogen level of approximately 10 to 20 percent.

Abstract: A method of making a magnetic random access memory device comprises forming a magnetic tunnel junction on an electrode, the magnetic tunnel junction comprising a reference layer positioned in contact with the electrode, a tunnel barrier layer arranged on the reference layer, and a free layer arranged on the tunnel barrier layer; and depositing an encapsulating layer on and along sidewalls of the magnetic tunnel junction at a temperature of 40 to 60° C. using remote microwave plasma deposition wherein the encapsulation layer comprises silicon and nitrogen. An MRAM device made by the aforementioned method is also disclosed.

Abstract: A method of making a magnetic random access memory device comprises forming a magnetic tunnel junction on an electrode, the magnetic tunnel junction comprising a reference layer positioned in contact with the electrode, a tunnel barrier layer arranged on the reference layer, and a free layer arranged on the tunnel barrier layer; and depositing an encapsulating layer on and along sidewalls of the magnetic tunnel junction at a temperature of 40 to 60° C. using remote microwave plasma deposition wherein the encapsulation layer comprises silicon and nitrogen. An MRAM device made by the aforementioned method is also disclosed.