Abstract: Techniques facilitating blockchain ledgers of material spectral signatures for supply chain integrity management are provided. In one example, a computer-implemented method comprises validating, by a device operatively coupled to a processor, spectral signature data associated with a material, resulting in validated spectral signature data; and generating, by the device, a set of information corresponding to a transaction of the material in a blockchain associated with the material, wherein the set of information is related to the validated spectral signature data. In some embodiments, the computer-implemented method further comprises authenticating, by the device, a first party device associated with a first party to the transaction and a second party device associated with a second party to the transaction and including identities of the first party and the second party as indicated by the respective party devices in the set of information.

Abstract: The present invention related to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.

Abstract: Techniques facilitating blockchain ledgers of material spectral signatures for supply chain integrity management are provided. In one example, a computer-implemented method comprises validating, by a device operatively coupled to a processor, spectral signature data associated with a material, resulting in validated spectral signature data; and generating, by the device, a set of information corresponding to a transaction of the material in a blockchain associated with the material, wherein the set of information is related to the validated spectral signature data. In some embodiments, the computer-implemented method further comprises authenticating, by the device, a first party device associated with a first party to the transaction and a second party device associated with a second party to the transaction and including identities of the first party and the second party as indicated by the respective party devices in the set of information.

Abstract: Techniques facilitating blockchain ledgers of material spectral signatures for supply chain integrity management are provided. In one example, a computer-implemented method comprises validating, by a device operatively coupled to a processor, spectral signature data associated with a material, resulting in validated spectral signature data; and generating, by the device, a set of information corresponding to a transaction of the material in a blockchain associated with the material, wherein the set of information is related to the validated spectral signature data. In some embodiments, the computer-implemented method further comprises authenticating, by the device, a first party device associated with a first party to the transaction and a second party device associated with a second party to the transaction and including identities of the first party and the second party as indicated by the respective party devices in the set of information.

Abstract: The present invention relates to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.

Abstract: Techniques facilitating blockchain ledgers of material spectral signatures for supply chain integrity management are provided. In one example, a computer-implemented method comprises validating, by a device operatively coupled to a processor, spectral signature data associated with a material, resulting in validated spectral signature data; and generating, by the device, a set of information corresponding to a transaction of the material in a blockchain associated with the material, wherein the set of information is related to the validated spectral signature data. In some embodiments, the computer-implemented method further comprises authenticating, by the device, a first party device associated with a first party to the transaction and a second party device associated with a second party to the transaction and including identities of the first party and the second party as indicated by the respective party devices in the set of information.

Abstract: The present invention related to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.

Abstract: Techniques facilitating blockchain ledgers of material spectral signatures for supply chain integrity management are provided. In one example, a computer-implemented method comprises validating, by a device operatively coupled to a processor, spectral signature data associated with a material, resulting in validated spectral signature data; and generating, by the device, a set of information corresponding to a transaction of the material in a blockchain associated with the material, wherein the set of information is related to the validated spectral signature data. In some embodiments, the computer-implemented method further comprises authenticating, by the device, a first party device associated with a first party to the transaction and a second party device associated with a second party to the transaction and including identities of the first party and the second party as indicated by the respective party devices in the set of information.

Abstract: Techniques facilitating blockchain ledgers of material spectral signatures for supply chain integrity management are provided. In one example, a computer-implemented method comprises validating, by a device operatively coupled to a processor, spectral signature data associated with a material, resulting in validated spectral signature data; and generating, by the device, a set of information corresponding to a transaction of the material in a blockchain associated with the material, wherein the set of information is related to the validated spectral signature data. In some embodiments, the computer-implemented method further comprises authenticating, by the device, a first party device associated with a first party to the transaction and a second party device associated with a second party to the transaction and including identities of the first party and the second party as indicated by the respective party devices in the set of information.

Abstract: The present invention relates to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.

Abstract: The present invention relates to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.

Abstract: A method is disclosed for preparing a surface of a Group III-Group V compound semiconductor for epitaxial deposition. The III-V semiconductor surface is treated with boron (B) at a temperature of between about 250° C. and about 350° C. A suitable form for supplying B for the surface treatment is diborane. The B treatment can be followed by epitaxial growth, for instance by a Group IV semiconductor, at temperatures similar to those of the B treatment. The method yields high quality heterojunction, suitable for fabricating a large variety of device structures.

Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Abstract: A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low concentrations of oxygen and water each less than 10 ppm. A material is also described by using the method with a dielectric constant of not more than 2.8. The invention overcomes the problem of forming films with low biaxial stress less than 46 MPa.

Abstract: A method is disclosed for preparing a surface of a Group III-Group V compound semiconductor for epitaxial deposition. The III-V semiconductor surface is treated with boron (B) at a temperature of between about 250° C. and about 350° C. A suitable form for supplying B for the surface treatment is diborane. The B treatment can be followed by epitaxial growth, for instance by a Group IV semiconductor, at temperatures similar to those of the B treatment. The method yields high quality heterojunction, suitable for fabricating a large variety of device structures.

Abstract: A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low concentrations of oxygen and water each less than 10 ppm. A material is also described by using the method with a dielectric constant of not more than 2.8. The invention overcomes the problem of forming films with low biaxial stress less than 46 MPa.

Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Abstract: A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low concentrations of oxygen and water each less than 10 ppm. A material is also described by using the method with a dielectric constant of not more than 2.8. The invention overcomes the problem of forming films with low biaxial stress less than 46 MPa.

Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.