Patents by Inventor Deborah J. Riley
Deborah J. Riley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11417646Abstract: An integrated circuit formed on a silicon substrate includes an NMOS transistor with n-channel raised source and drain (NRSD) layers adjacent to a gate of the NMOS transistor, a PMOS transistor with SiGe stressors in the substrate adjacent to a gate of the PMOS transistor, and an NPN heterojunction bipolar transistor (NHBT) with a p-type SiGe base formed in the substrate and an n-type silicon emitter formed on the SiGe base. The SiGe stressors and the SiGe base are formed by silicon-germanium epitaxy. The NRSD layers and the silicon emitter are formed by silicon epitaxy.Type: GrantFiled: June 3, 2016Date of Patent: August 16, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Manoj Mehrotra, Terry J. Bordelon, Deborah J. Riley
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Publication number: 20180308977Abstract: An integrated circuit and method having a first PMOS transistor with extension and pocket implants and with SiGe source and drains and having a second PMOS transistor without extension and without pocket implants and with SiGe source and drains. The distance from the SiGe source and drains to the gate of the first PMOS transistor is greater than the distance from the SiGe source and drains to the gate of the second PMOS transistor and the turn on voltage of the first PMOS transistor is at least 50 mV higher than the turn on voltage of the second PMOS transistor.Type: ApplicationFiled: July 2, 2018Publication date: October 25, 2018Inventors: Younsung CHOI, Deborah J. RILEY
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Patent number: 10026837Abstract: An integrated circuit and method having a first PMOS transistor with extension and pocket implants and with SiGe source and drains and having a second PMOS transistor without extension and without pocket implants and with SiGe source and drains. The distance from the SiGe source and drains to the gate of the first PMOS transistor is greater than the distance from the SiGe source and drains to the gate of the second PMOS transistor and the turn on voltage of the first PMOS transistor is at least 50 mV higher than the turn on voltage of the second PMOS transistor.Type: GrantFiled: September 3, 2015Date of Patent: July 17, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Younsung Choi, Deborah J. Riley
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Publication number: 20170069755Abstract: An integrated circuit and method having a first PMOS transistor with extension and pocket implants and with SiGe source and drains and having a second PMOS transistor without extension and without pocket implants and with SiGe source and drains. The distance from the SiGe source and drains to the gate of the first PMOS transistor is greater than the distance from the SiGe source and drains to the gate of the second PMOS transistor and the turn on voltage of the first PMOS transistor is at least 50 mV higher than the turn on voltage of the second PMOS transistor.Type: ApplicationFiled: September 3, 2015Publication date: March 9, 2017Inventors: Younsung CHOI, Deborah J. RILEY
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Publication number: 20160284691Abstract: An integrated circuit formed on a silicon substrate includes an NMOS transistor with n-channel raised source and drain (NRSD) layers adjacent to a gate of the NMOS transistor, a PMOS transistor with SiGe stressors in the substrate adjacent to a gate of the PMOS transistor, and an NPN heterojunction bipolar transistor (NHBT) with a p-type SiGe base formed in the substrate and an n-type silicon emitter formed on the SiGe base. The SiGe stressors and the SiGe base are formed by silicon-germanium epitaxy. The NRSD layers and the silicon emitter are formed by silicon epitaxy.Type: ApplicationFiled: June 3, 2016Publication date: September 29, 2016Inventors: Manoj MEHROTRA, Terry J. BORDELON, Deborah J. RILEY
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Patent number: 9385117Abstract: An integrated circuit formed on a silicon substrate includes an NMOS transistor with n-channel raised source and drain (NRSD) layers adjacent to a gate of the NMOS transistor, a PMOS transistor with SiGe stressors in the substrate adjacent to a gate of the PMOS transistor, and an NPN heterojunction bipolar transistor (NHBT) with a p-type SiGe base formed in the substrate and an n-type silicon emitter formed on the SiGe base. The SiGe stressors and the SiGe base are formed by silicon-germanium epitaxy. The NRSD layers and the silicon emitter are formed by silicon epitaxy.Type: GrantFiled: December 17, 2014Date of Patent: July 5, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Manoj Mehrotra, Terry J. Bordelon, Jr., Deborah J. Riley
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Publication number: 20150187755Abstract: An integrated circuit formed on a silicon substrate includes an NMOS transistor with n-channel raised source and drain (NRSD) layers adjacent to a gate of the NMOS transistor, a PMOS transistor with SiGe stressors in the substrate adjacent to a gate of the PMOS transistor, and an NPN heterojunction bipolar transistor (NHBT) with a p-type SiGe base formed in the substrate and an n-type silicon emitter formed on the SiGe base. The SiGe stressors and the SiGe base are formed by silicon-germanium epitaxy. The NRSD layers and the silicon emitter are formed by silicon epitaxy.Type: ApplicationFiled: December 17, 2014Publication date: July 2, 2015Inventors: Manoj MEHROTRA, Terry J. BORDELON, JR., Deborah J. RILEY
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Patent number: 8927385Abstract: An integrated circuit having a replacement gate MOS transistor and a polysilicon resistor may be formed by removing a portion at the top surface of the polysilicon layer in the resistor area. A subsequently formed gate etch hard mask includes a MOS hard mask segment over a MOS sacrificial gate and a resistor hard mask segment over a resistor body. The resistor body is thinner than the MOS sacrificial gate. During the gate replacement process sequence, the MOS hard mask segment is removed, exposing the MOS sacrificial gate while at least a portion of the resistor hard mask segment remains over the resistor body. The MOS sacrificial gate is replaced by a replacement gate while the resistor body is not replaced.Type: GrantFiled: December 17, 2012Date of Patent: January 6, 2015Assignee: Texas Instruments IncorporatedInventors: Mahalingam Nandakumar, Deborah J. Riley, Amitabh Jain
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Patent number: 8877581Abstract: An integrated circuit (IC) includes a plurality of strained metal oxide semiconductor (MOS) devices that include a semiconductor surface having a first doping type, a gate electrode stack over a portion of the semiconductor surface, and source/drain recesses that extend into the semiconductor surface and are framed by semiconductor surface interface regions on opposing sides of the gate stack. A first epitaxial strained alloy layer (rim) is on the semiconductor surface interface regions, and is doped with the first doping type. A second epitaxial strained alloy layer is on the rim and is doped with a second doping type that is opposite to the first doping type that is used to form source/drain regions.Type: GrantFiled: August 13, 2010Date of Patent: November 4, 2014Assignee: Texas Instruments IncorporatedInventors: Amitabh Jain, Deborah J. Riley
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Publication number: 20140167182Abstract: An integrated circuit having a replacement gate MOS transistor and a polysilicon resistor may be formed by removing a portion at the top surface of the polysilicon layer in the resistor area. A subsequently formed gate etch hard mask includes a MOS hard mask segment over a MOS sacrificial gate and a resistor hard mask segment over a resistor body. The resistor body is thinner than the MOS sacrificial gate. During the gate replacement process sequence, the MOS hard mask segment is removed, exposing the MOS sacrificial gate while at least a portion of the resistor hard mask segment remains over the resistor body. The MOS sacrificial gate is replaced by a replacement gate while the resistor body is not replaced.Type: ApplicationFiled: December 17, 2012Publication date: June 19, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Mahalingam Nandakumar, Deborah J. Riley, Amitabh Jain
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Patent number: 8691644Abstract: A method of forming stressed-channel NMOS transistors and strained-channel PMOS transistors forms p-type source and drain regions before an n-type source and drain dopant is implanted and a stress memorization layer is formed, thereby reducing the stress imparted to the n-channel of the PMOS transistors. In addition, a non-conductive layer is formed after the p-type source and drain regions are formed, but before the n-type dopant is implanted. The non-conductive layer allows shallower n-type implants to be realized, and also serves as a buffer layer for the stress memorization layer.Type: GrantFiled: July 5, 2012Date of Patent: April 8, 2014Assignee: Texas Instruments IncorporatedInventors: Seung-Chul Song, Amitabh Jain, Deborah J. Riley
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Publication number: 20140011340Abstract: A method of forming stressed-channel NMOS transistors and strained-channel PMOS transistors forms p-type source and drain regions before an n-type source and drain dopant is implanted and a stress memorization layer is formed, thereby reducing the stress imparted to the n-channel of the PMOS transistors. In addition, a non-conductive layer is formed after the p-type source and drain regions are formed, but before the n-type dopant is implanted. The non-conductive layer allows shallower n-type implants to be realized, and also serves as a buffer layer for the stress memorization layer.Type: ApplicationFiled: July 5, 2012Publication date: January 9, 2014Inventors: Seung-Chul Song, Amitabh Jain, Deborah J. Riley
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Patent number: 8470707Abstract: A process for forming an integrated circuit with reduced sidewall spacers to enable improved silicide formation between minimum spaced transistor gates. A process for forming an integrated circuit with reduced sidewall spacers by first forming sidewall spacer by etching a sidewall dielectric and stopping on an etch stop layer, implanting source and drain dopants self aligned to the sidewall spacers, followed by removing a portion of the sidewall dielectric and removing the etch stop layer self aligned to the reduced sidewall spacers prior to forming silicide.Type: GrantFiled: November 2, 2011Date of Patent: June 25, 2013Assignee: Texas Instruments IncorporatedInventors: Weize Xiong, Deborah J. Riley
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Publication number: 20120108027Abstract: A process for forming an integrated circuit with reduced sidewall spacers to enable improved silicide formation between minimum spaced transistor gates. A process for forming an integrated circuit with reduced sidewall spacers by first forming sidewall spacer by etching a sidewall dielectric and stopping on an etch stop layer, implanting source and drain dopants self aligned to the sidewall spacers, followed by removing a portion of the sidewall dielectric and removing the etch stop layer self aligned to the reduced sidewall spacers prior to forming silicide.Type: ApplicationFiled: November 2, 2011Publication date: May 3, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Weize Xiong, Deborah J. Riley
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Patent number: 8043921Abstract: A method of removing silicon nitride over a semiconductor surface for forming shallow junctions. Sidewall spacers are formed along sidewalls of a gate stack that together define lightly doped drain (LDD) regions or source/drain (S/D) regions. At least one of the sidewall spacers, LDD regions and S/D regions include an exposed silicon nitride layer. The LDD or S/D regions include a protective dielectric layer formed directly on the semiconductor surface. Ion implanting implants the LDD regions or S/D regions using the sidewall spacers as implant masks. The exposed silicon nitride layer is selectively removed, wherein the protective dielectric layer when the sidewall spacers include the exposed silicon nitride layer, or a replacement protective dielectric layer formed directly on the semiconductor surface after ion implanting when the LDD or S/D regions include the exposed silicon nitride layer, protects the LDD or S/D regions from dopant loss due to etching during selectively removing.Type: GrantFiled: March 25, 2010Date of Patent: October 25, 2011Assignee: Texas Instruments IncorporatedInventors: Brian K. Kirkpatrick, Deborah J. Riley
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Publication number: 20110042753Abstract: An integrated circuit (IC) includes a plurality of strained metal oxide semiconductor (MOS) devices that include a semiconductor surface having a first doping type, a gate electrode stack over a portion of the semiconductor surface, and source/drain recesses that extend into the semiconductor surface and are framed by semiconductor surface interface regions on opposing sides of the gate stack. A first epitaxial strained alloy layer (rim) is on the semiconductor surface interface regions, and is doped with the first doping type. A second epitaxial strained alloy layer is on the rim and is doped with a second doping type that is opposite to the first doping type that is used to form source/drain regions.Type: ApplicationFiled: August 13, 2010Publication date: February 24, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Amitabh Jain, Deborah J. Riley
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Publication number: 20100248440Abstract: A method of removing silicon nitride over a semiconductor surface for forming shallow junctions. Sidewall spacers are formed along sidewalls of a gate stack that together define lightly doped drain (LDD) regions or source/drain (S/D) regions. At least one of the sidewall spacers, LDD regions and S/D regions include an exposed silicon nitride layer. The LDD or S/D regions include a protective dielectric layer formed directly on the semiconductor surface. Ion implanting implants the LDD regions or S/D regions using the sidewall spacers as implant masks. The exposed silicon nitride layer is selectively removed, wherein the protective dielectric layer when the sidewall spacers include the exposed silicon nitride layer, or a replacement protective dielectric layer formed directly on the semiconductor surface after ion implanting when the LDD or S/D regions include the exposed silicon nitride layer, protects the LDD or S/D regions from dopant loss due to etching during selectively removing.Type: ApplicationFiled: March 25, 2010Publication date: September 30, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Brian K. Kirkpatrick, Deborah J. Riley
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Publication number: 20100167519Abstract: A method for fabricating a CMOS integrated circuit (IC) includes the step of providing a substrate having a semiconductor surface. A gate stack including a metal gate electrode on a metal including high-k dielectric layer is formed on the semiconductor surface. Dry etching is used to pattern the gate stack to define a patterned gate electrode stack having exposed sidewalls of the metal gate electrode. The dry etching forms post etch residuals some of which are deposited on the substrate. The substrate including the patterned gate electrode stack is exposed to a solution cleaning sequence including a first clean step including a first acid and a fluoride for removing at least a portion of the post etch residuals, wherein the first clean step has a high selectivity to avoid etching the exposed sidewalls of the metal gate electrode. A second clean after the first clean consists essentially of a fluoride which removes residual high-k material on the semiconductor surface.Type: ApplicationFiled: December 26, 2008Publication date: July 1, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: BRIAN K. KIRKPATRICK, JINHAN CHOI, DEBORAH J. RILEY
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Patent number: 7732284Abstract: A method for fabricating a CMOS integrated circuit (IC) includes the step of providing a substrate having a semiconductor surface. A gate stack including a metal gate electrode on a metal including high-k dielectric layer is formed on the semiconductor surface. Dry etching is used to pattern the gate stack to define a patterned gate electrode stack having exposed sidewalls of the metal gate electrode. The dry etching forms post etch residuals some of which are deposited on the substrate. The substrate including the patterned gate electrode stack is exposed to a solution cleaning sequence including a first clean step including a first acid and a fluoride for removing at least a portion of the post etch residuals, wherein the first clean step has a high selectivity to avoid etching the exposed sidewalls of the metal gate electrode. A second clean after the first clean consists essentially of a fluoride which removes residual high-k material on the semiconductor surface.Type: GrantFiled: December 26, 2008Date of Patent: June 8, 2010Assignee: Texas Instruments IncorporatedInventors: Brian K. Kirkpatrick, Jinhan Choi, Deborah J. Riley
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Publication number: 20100032813Abstract: A semiconductor device, such as an integrated circuit, has an oxide chemically grown on a silicon surface, and densified by annealing at, e.g., 950° C. for 4 to 5 seconds in an N2 ambient, or at an equivalent thermal profile in a similarly non-oxidizing ambient. The densified chemical oxide has an etch rate the same as that of thermally grown silicon dioxide in common etchants used in IC fabrication.Type: ApplicationFiled: August 10, 2009Publication date: February 11, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Deborah J. Riley, Haowen Bu, Brian Edward Hornung