Abstract: While displaying an application user interface, a device detects a first input to an input device of the one or more input devices, the input device provided on a housing of the device that includes the one or more display generation components. In response to detecting the first input, the device replaces display of at least a portion of the application user interface by displaying a home menu user interface via the one or more display generation components. While displaying the home menu user interface, the device detects a second input to the input device provided on the housing of the device; and in response to detecting the second input to the input device provided on the housing of the device: the device dismisses the home menu user interface.

Abstract: A wearable device, while a respective session is active in a respective application, detects a first signal indicating that the wearable device in no longer being worn. In response, the wearable device causes the respective session of the respective application to become inactive. While the respective application is inactive, the wearable device detects a second signal indicating that the wearable device is being put on, and in response to detecting the second signal, in accordance with a determination that respective criteria are met, the wearable device resumes the respective session of the respective application. Further, in accordance with a determination that respective criteria are not met, the wearable device forgoes resuming the respective session of the respective application, wherein the respective criteria include a criterion that is met when a current user of the wearable device is determined to be an authorized user of the wearable device.

Abstract: A clock relationship based re-convergence analysis method includes receiving, by a processing device, a register-transfer level (RTL) description of a design relating to an integrated circuit (IC). The method further includes identifying one or more clock domain crossing (CDC) synchronizers in the RTL description of the design, and generating a levelized topological abstract graph (LTAG) including a network of nodes. Each node includes a CDC synchronizer. The method further includes traversing the LTAG starting from a first output of the one or more CDC synchronizers, and responsive to determining that a first CDC synchronizer of the one or more CDC synchronizers is converging with a second CDC synchronizer, identifying a first potential convergence violation associated with the first CDC synchronizer and the second CDC synchronizer.

Abstract: A system, method, and computer program product are disclosed. The method includes receiving a first text unit, extracting features from the first text unit, receiving a second text unit, extracting features from the second text unit, receiving a portion comprising the first text unit and the second text unit, and aggregating the features extracted from the first text unit and the features extracted from the second text unit. The method also includes generating a set of scores for the first text unit, the second text unit, and the portion, and based on the set of scores, selecting at least one ground truth candidate from the first text unit, the second text unit, and the portion. Additionally, the method includes determining that the at least one ground truth candidate includes at least one confirmed ground truth, and adding the at least one confirmed ground truth to a ground truth repository.

Abstract: Sets of objects may be received which are desired to be stored using a nested hash map, where the nested hash map may include multiple levels, and where each set of objects in the sets of objects may correspond to a level in the nested hash map. The nested hash map may be created from a bottom level of the nested hash map to a top level of the nested hash map, which may include: creating a first hash map at a first level of the nested hash map, creating a first shared pointer which points to the first hash map, and creating a second hash map at a second level which is immediately above the first level, where the second hash map maps at least one object to the first shared pointer.

Abstract: The technology disclosed relates to verifying metastability for a clock domain crossing (CDC) in a circuit design. The technology disclosed may include, for a destination clock domain in the circuit design, creating a circuit graph based, at least in part, on the circuit design. The circuit graph includes start points and stop points. The start points may be data inputs, clocks, and enables of the destination clock domain. The stop points may be synchronizer outputs of the destination clock domain and a source clock domain in the circuit design. The technology disclosed may also include traversing the circuit graph to mark all graph nodes that reside in a source-destination path of the CDC. Based on the marked graph nodes, the start points, and the stop points, the technology disclosed may also include propagating destination domain qualifiers on the circuit graph within an allowed sequential depth.

Abstract: The technology disclosed relates to verifying metastability for a clock domain crossing (CDC) in a circuit design. The technology disclosed may include, for a destination clock domain in the circuit design, creating a circuit graph based, at least in part, on the circuit design. The circuit graph includes start points and stop points. The start points may be data inputs, clocks, and enables of the destination clock domain. The stop points may be synchronizer outputs of the destination clock domain and a source clock domain in the circuit design. The technology disclosed may also include traversing the circuit graph to mark all graph nodes that reside in a source-destination path of the CDC. Based on the marked graph nodes, the start points, and the stop points, the technology disclosed may also include propagating destination domain qualifiers on the circuit graph within an allowed sequential depth.

Abstract: Clock-domain crossing (CDC) verification for system on chip (SoC) integrated circuits (IC) can be time consuming and complex, especially as the size of the SoC and the complexity of the modules of which it comprises increase. A bottom-up verification process includes the replacement of a CDC verified module by an abstracted model of the module with constraints defined on the boundaries of the module. Performing the process in a hierarchic manner from bottom upwards allows for faster verification of modules higher in the hierarchy as at least portions thereof are replaced with the abstracted modules.

Abstract: Clock-domain crossing (CDC) verification for system on chip (SoC) integrated circuits (IC) can be time consuming and complex, especially as the size of the SoC and the complexity of the modules of which it comprises increase. A bottom-up verification process includes the replacement of a CDC verified module by an abstracted model of the module with constraints defined on the boundaries of the module. Performing the process in a hierarchic manner from bottom upwards allows for faster verification of modules higher in the hierarchy as at least portions thereof are replaced with the abstracted modules.