Abstract: This disclosure describes techniques for addressing and/or accounting for path failures (e.g., congestion, link failures, disconnections, or other types of failures) within a network environment. In one example, this disclosure describes a method that includes receiving, by a node connected to a plurality of interconnected nodes, a network packet to be forwarded to a destination node; identifying, by a forwarding plane within the node, a first link along a path to the destination node; determining, by the forwarding plane, that the first link is inoperable; storing, by the node and within the network packet, data identifying the node as having been visited; identifying, by the forwarding plane and from among the plurality of egress links from the node, a second link that is operable and is along an alternative path to the destination node; and transmitting the network packet over the second link.

Abstract: A new processing architecture is described that utilizes a data processing unit (DPU). Unlike conventional compute models that are centered around a central processing unit (CPU), the DPU that is designed for a data-centric computing model in which the data processing tasks are centered around the DPU. The DPU may be viewed as a highly programmable, high-performance I/O and data-processing hub designed to aggregate and process network and storage I/O to and from other devices. The DPU comprises a network interface to connect to a network, one or more host interfaces to connect to one or more application processors or storage devices, and a multi-core processor with two or more processing cores executing a run-to-completion data plane operating system and one or more processing cores executing a multi-tasking control plane operating system. The data plane operating system is configured to support software functions for performing the data processing tasks.

Abstract: One example provides an integrated computing device, comprising one or more computing clusters, and one or more network controllers, each network controller comprising a local data notification queue to queue send message notifications originating from the computing clusters on the integrated computing device, a remote data notification queue to queue receive message notifications originating from network controllers on remote integrated computing devices, a local no-data notification queue to queue receive message notifications originating from computing clusters on the integrated computing device, and a connection scheduler configured to schedule sending of data from memory on the integrated computing device when a send message notification in the local data notification queue is matched with a receive message notification in the remote data notification queue, and to schedule sending of receive message notifications from the local no-data notification queue.

Abstract: A new processing architecture is described that utilizes a data processing unit (DPU). Unlike conventional compute models that are centered around a central processing unit (CPU), the DPU that is designed for a data-centric computing model in which the data processing tasks are centered around the DPU. The DPU may be viewed as a highly programmable, high-performance I/O and data-processing hub designed to aggregate and process network and storage I/O to and from other devices. The DPU comprises a network interface to connect to a network, one or more host interfaces to connect to one or more application processors or storage devices, and a multi-core processor with two or more processing cores executing a run-to-completion data plane operating system and one or more processing cores executing a multi-tasking control plane operating system. The data plane operating system is configured to support software functions for performing the data processing tasks.

Abstract: A network system for a data center is described in which an access node sprays a data flow of packets over a logical tunnel to another access node. In one example, a method comprises establishing, by a plurality of access nodes, a logical tunnel over a plurality of data paths across a switch fabric between a source access node and a destination access node included within the plurality of access nodes, wherein the source access node is coupled to a source network device; and spraying, by the source access node, a data flow of packets over the logical tunnel to the destination access node, wherein the source access node receives the data flow of packets from the source network device, and wherein spraying the data flow of packets includes directing each of the packets within the data flow to a least loaded data path.

Abstract: A new processing architecture is described in which a data processing unit (DPU) is utilized within a device. Unlike conventional compute models that are centered around a central processing unit (CPU), example implementations described herein leverage a DPU that is specially designed and optimized for a data-centric computing model in which the data processing tasks are centered around, and the primary responsibility of, the DPU. For example, various data processing tasks, such as networking, security, and storage, as well as related work acceleration, distribution and scheduling, and other such tasks are the domain of the DPU. The DPU may be viewed as a highly programmable, high-performance input/output (I/O) and data-processing hub designed to aggregate and process network and storage I/O to and from multiple other components and/or devices. This frees resources of the CPU, if present, for computing-intensive tasks.

Abstract: This disclosure describes techniques for performing communications between devices using various aspects of Ethernet standards. As further described herein, a protocol is disclosed that may be used for communications between devices, where the communications take place over a physical connection complying with Ethernet standards. Such a protocol may enable reliable and in-order delivery of frames between devices, while following Ethernet physical layer rules, Ethernet symbol encoding, Ethernet lane alignment, and/or Ethernet frame formats.

Abstract: A network system for a data center is described in which an access node sprays a data flow of packets over a logical tunnel to another access node. In one example, a method comprises establishing, by a plurality of access nodes, a logical tunnel over a plurality of data paths across a switch fabric between a source access node and a destination access node included within the plurality of access nodes, wherein the source access node is coupled to a source network device; and spraying, by the source access node, a data flow of packets over the logical tunnel to the destination access node, wherein the source access node receives the data flow of packets from the source network device, and wherein spraying the data flow of packets includes directing each of the packets within the data flow to a least loaded data path.

Abstract: Hardware semaphores are utilized to increase the speed with which preconditions are evaluated. On an individual basis, each hardware semaphore can implement a binary semaphore or a counting semaphore. Collections of hardware semaphores can be chained together to implement a chain semaphore that can support multiple conditionals. In addition, hardware semaphores can have the capability, not only of generating an interrupt, but, in addition, being able to generate commands, such as to other semaphores. The implementation of a chain semaphore spanning multiple hardware semaphores can be performed by a compiler at compile time or at run time. An integrated circuit chip can comprise multiple execution units, such as processing cores, and individual ones of the execution units can be associated with multiple hardware semaphores, such as in the form of hardware semaphore arrays. A dedicated network-on-chip enables hardware semaphore communication.

Abstract: This disclosure describes techniques for performing communications between devices using various aspects of Ethernet standards. As further described herein, a protocol is disclosed that may be used for communications between devices, where the communications take place over a physical connection complying with Ethernet standards. Such a protocol may enable reliable and in-order delivery of frames between devices, while following Ethernet physical layer rules, Ethernet symbol encoding, Ethernet lane alignment, and/or Ethernet frame formats.

Abstract: A network system for a data center. In one example, a method comprises establishing, by a plurality of access nodes, a logical tunnel over a plurality of data paths across a switch fabric between a source access node and a destination access node included within the plurality of access nodes, wherein the source access node is coupled to a source network device; and spraying, by the source access node, a data flow of packets over the logical tunnel to the destination access node, wherein the source access node receives the data flow of packets from the source network device, and wherein spraying the data flow of packets includes directing each of the packets within the data flow to one of the data paths based on an amount of data previously transmitted on each of the plurality of data paths.

Abstract: Techniques for detecting path failures and reducing packet loss as a result of such failures are described for use within a data center or other environment. For example, a source and/or destination access node may create and/or maintain information about health and/or connectivity for a plurality of ports or paths between the source and destination device and core switches. The source access node may spray packets over a number of paths between the source access node and the destination access node. The source access node may use the information about connectivity for the paths between the source or destination access nodes and the core switches to limit the paths over which packets are sprayed. The source access node may spray packets over paths between the source access node and the destination access node that are identified as healthy, while avoiding paths that have been identified as failed.

Abstract: Systems and methods for sending and receiving messages, including training data, using a multi-path packet spraying protocol are described. A method includes segmenting a message into a set of data packets comprising training data. The method further includes initiating transmission of the set of data packets to a receiving node. The method further includes spraying the set of data packets across the switch fabric in accordance with the multi-path spraying protocol such that depending upon a value of a fabric determination field associated with a respective data packet, the respective data packet can traverse via any one of a plurality of paths offered by the switch fabric for a connection between the sending node to the receiving node. The method further includes initiating transmission of synchronization packets to the receiving node, where unlike the set of data packets, the synchronization packets are not sprayed across the switch fabric.

Abstract: A network system for a data center is described in which a switch fabric may provide full mesh interconnectivity such that any servers may communicate packet data to any other of the servers using any of a number of parallel data paths. Moreover, according to the techniques described herein, edge-positioned access nodes, optical permutation devices and core switches of the switch fabric may be configured and arranged in a way such that the parallel data paths provide single L2/L3 hop, full mesh interconnections between any pairwise combination of the access nodes, even in massive data centers having tens of thousands of servers. The plurality of optical permutation devices permute communications across the optical ports based on wavelength so as to provide, in some cases, full-mesh optical connectivity between edge-facing ports and core-facing ports.

Abstract: Techniques for detecting path failures and reducing packet loss as a result of such failures are described for use within a data center or other environment. For example, a source and/or destination access node may create and/or maintain information about health and/or connectivity for a plurality of ports or paths between the source and destination device and core switches. The source access node may spray packets over a number of paths between the source access node and the destination access node. The source access node may use the information about connectivity for the paths between the source or destination access nodes and the core switches to limit the paths over which packets are sprayed. The source access node may spray packets over paths between the source access node and the destination access node that are identified as healthy, while avoiding paths that have been identified as failed.

Abstract: Embodiments of the present disclosure include techniques for processing neural networks. Various forms of parallelism may be implemented using topology that combines sequences of processors. In one embodiment, the present disclosure includes a computer system comprising a plurality of processor groups, the processor groups each comprising a plurality of processors. A plurality of network switches are coupled to subsets of the plurality of processor groups. A subset of the processors in the processor groups may be configurable to form sequences, and the network switches are configurable to form at least one sequence across one or more of the plurality of processor groups to perform neural network computations. Various alternative configurations for creating Hamiltonian cycles are disclosed to support data parallelism, pipeline parallelism, layer parallelism, or combinations thereof.

Abstract: An access node that can be configured and optimized to perform input and output (I/O) tasks, such as storage and retrieval of data to and from network devices (such as solid state drives), networking, data processing, and the like. For example, the access node may be configured to receive data to be processed, wherein the access node includes a plurality of processing cores, a data network fabric, and a control network fabric; receive, over the control network fabric, a work unit message indicating a processing task to be performed a processing core; and process the work unit message, wherein processing the work unit message includes retrieving data associated with the work unit message over the data network fabric.

Abstract: Hardware semaphores are utilized to increase the speed with which preconditions are evaluated. On an individual basis, each hardware semaphore can implement a binary semaphore or a counting semaphore. Collections of hardware semaphores can be chained together to implement a chain semaphore that can support multiple conditionals. In addition, hardware semaphores can have the capability, not only of generating an interrupt, but, in addition, being able to generate commands, such as to other semaphores. The implementation of a chain semaphore spanning multiple hardware semaphores can be performed by a compiler at compile time or at run time. An integrated circuit chip can comprise multiple execution units, such as processing cores, and individual ones of the execution units can be associated with multiple hardware semaphores, such as in the form of hardware semaphore arrays. A dedicated network-on-chip enables hardware semaphore communication.

Abstract: The present disclosure relates to systems, methods, and computer-readable media for data from a first multi-dimensional memory block to a second multi-dimensional memory block. For example, systems described herein facilitate transferring data between memory blocks having different shapes from one another. The systems described herein facilitate transferring data between different shaped memory blocks by identifying shape properties and other characteristics of the data and generating a plurality of network packets having control data based on the identified shape properties and other characteristics. This data included within the network packets enables memory controllers to determine memory addresses on a destination memory block to write data from the network packets. Features described herein facilitate efficient transfer of data without generating a linearized copy that relies on constant availability of significant memory resources.

Abstract: The present disclosure relates to systems for generating network packets that facilitate reliable and secure transmission of data between computing devices. For example, systems described herein involve generating a network packet in which a transport layer and security layer are implemented within an authentication header of the network packet. Information from the authentication header may be evaluated by a receiving device using a security key to compute an integrity check vector and an initialization vector to determine that a network packet has been provided in a correct order as well as check against a variety of security threats.