Abstract: A system and method for realizing a building system is disclosed. In an embodiment, a holistic approach to a complex building system involves using high-productivity high-performance computing resources, such as cloud services, to manage a complex building system from building inception through to building operation. Because high-productivity high-performance computing resources are used, modeling, optimization, simulation, and verification can be performed from a single platform on a scale which heretofore has not been applied to complex building systems. Additionally, the holistic approach to complex building systems involves using a centralized database to manage all of the information related to a building system.

Abstract: A system and method for realizing a building system is disclosed. In an embodiment, a holistic approach to a complex building system involves using high-productivity high-performance computing resources, such as cloud services, to manage a complex building system from building inception through to building operation. Because high-productivity high-performance computing resources are used, modeling, optimization, simulation, and verification can be performed from a single platform on a scale which heretofore has not been applied to complex building systems. Additionally, the holistic approach to complex building systems involves using a centralized database to manage all of the information related to a building system.

Abstract: A system and method for realizing a building system is disclosed. In an embodiment, a holistic approach to a complex building system involves using high-productivity high-performance computing resources, such as cloud services, to manage a complex building system from building inception through to building operation. Because high-productivity high-performance computing resources are used, modeling, optimization, simulation, and verification can be performed from a single platform on a scale which heretofore has not been applied to complex building systems. Additionally, the holistic approach to complex building systems involves using a centralized database to manage all of the information related to a building system.

Abstract: The flow of packet-based traffic is controlled to meet a desired rate by calculating, as a moving average, a current rate of packet-based traffic on a link, calculating the sum of the error between the calculated current rate and the desired rate, and determining whether or not packets can flow in response to the calculated sum of the error. When the sum of the error between the current rate and the desired rate indicates that the current rate is less than the desired rate, packets are allowed to flow and when the sum of the error indicates that the current rate is greater than the desired rate, packets are not allowed to flow. The magnitude of bursts can also be controlled by artificially controlling the minimum values of the current rate and the sum of the error. The flow control algorithm can be used for rate shaping or rate limiting.

Abstract: The flow of packet-based traffic is controlled to meet a desired rate by calculating, as a moving average, a current rate of packet-based traffic on a link, calculating the sum of the error between the calculated current rate and the desired rate, and determining whether or not packets can flow in response to the calculated sum of the error. When the sum of the error between the current rate and the desired rate indicates that the current rate is less than the desired rate, packets are allowed to flow and when the sum of the error indicates that the current rate is greater than the desired rate, packets are not allowed to flow. The magnitude of bursts can also be controlled by artificially controlling the minimum values of the current rate and the sum of the error. The flow control algorithm can be used for rate shaping or rate limiting.

Abstract: A method and apparatus for forwarding packets from contending queues of a multiport switch to an output of a finite bandwidth involve first prioritizing the contending queues into different priorities that relate to priorities of the packets that are being forwarded in the network. Bandwidth of the output is then allocated among the prioritized contending queues and the bandwidth of the output is consumed by the queued packets according to the allocated proportions. Any unconsumed bandwidth is distributed to the queues on a priority basis such that the highest priority queue is offered the unconsumed bandwidth first and lower priority queues are offered the remaining unconsumed bandwidth in priority order. An advantage of the invention is that queues are not starved of bandwidth by higher priority queues and unconsumed bandwidth is not wasted when there are not enough packets to consume an allocated portion of the output bandwidth.

Abstract: A microprocessor includes an instruction fetch unit, a branch prediction unit, and a decode unit. The instruction fetch unit is adapted to retrieve a plurality of program instructions. The program instructions include serialization initiating instructions and branch instructions. The branch prediction unit is adapted to generate branch predictions for the branch instructions, direct the instruction fetch unit to retrieve the program instructions in an order corresponding to the branch predictions, and redirect the instruction fetch unit based on a branch misprediction. The branch prediction unit is further adapted to store a redirect address corresponding to the branch misprediction. The decode unit is adapted to decode the program instructions into microcode.

Abstract: A clock throttling mechanism turns off certain processor components to minimize power consumption. The processor detects the issuance of certain bus cycles or the execution of certain instructions which typically cause the processor to be idle for a period of time. Control circuitry detects the existence of the instruction and/or bus cycle and shuts down the clock driving certain processor components during that idle period. The control circuitry then detects the occurrence or upcoming occurrence of an event to which the processor responds and becomes active. At detection of this event, the clock signal input to these components is then restarted such that the processor can continue normal execution.

Abstract: A microprocessor for use in a computer system which pipelines addresses for both burst and non-burst mode data transfers. By pipelining addresses, the microprocessor is able to increase the throughput of data transfers in the system. In the present invention, bits are used which may be programmed to disable and enable the address pipelining for the non-burst mode and burst mode transfers.

Abstract: An innovative protocol and system for implementing the same enables quick release of the bus by the master device, such as a CPU, to permit slave devices access to the bus. In one embodiment, the arbiter can select between the original hold protocol and quick hold protocol according to predetermined criteria which indicates that a low latency response is requested. Upon assertion of a QHOLD signal, the CPU issues a burst last signal to prematurely terminate outstanding burst transactions on the bus in a manner transparent to the slave devices. Once the outstanding bus cycles are complete, the CPU performs an internal backoff to immediately release the bus for access by the slave device requesting access. Any pending burst cycles which were terminated prematurely by the QHOLD signal, are subsequently restarted for the data not transacted by the CPU after the slave device completes access to the bus.