Patents by Inventor Deepak K. Pai
Deepak K. Pai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8549737Abstract: The present invention relates to a compliant leaded interposer for resiliently attaching and electrically connecting a ball grid array package to a circuit board. The interposer may include a substrate, a plurality of pads, and a plurality of pins. The plurality of pads may be positioned substantially on the top surface of the substrate and arranged in a predetermined pattern substantially corresponding to the solder ball pattern on the ball grid array package. The plurality of pins may be positioned substantially perpendicular to the substrate and may extend through the substrate and the plurality of pads. The interposer may be configured to attach the ball grid array package to the circuit board such that each of the solder balls on the ball grid array package contacts at least a portion the plurality of pins and at least a portion of the plurality of pads and such that the each of the plurality of pins also connects to a contact on the circuit board.Type: GrantFiled: March 22, 2010Date of Patent: October 8, 2013Assignee: General Dynamics Advanced Information Systems, Inc.Inventor: Deepak K. Pai
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Patent number: 8481862Abstract: The present invention relates to a connector system for resiliently attaching and electrically connecting an integrated circuit chip to a circuit board using a plurality of leads. Each of the plurality of leads are sized and arranged to form a curved body having a first leg and a second leg with a curved portion between the first leg and the second leg. The curved body of the leads may be C-shaped in accordance with the present invention. The plurality of leads may be formed from strips of copper foil or copper mesh folded to form the curved body. The plurality of leads may also be sized and arranged to support the integrated circuit chip in a generally flat arrangement relative to the circuit board with a maximum separation of about 0.016 inches or less between the integrated circuit chip and the circuit board.Type: GrantFiled: February 9, 2006Date of Patent: July 9, 2013Assignee: General Dynamics Advanced Information Systems, Inc.Inventors: Deepak K. Pai, Melvin Eric Graf
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Patent number: 8196291Abstract: A system method for manufacturing leads is provided. The method includes providing a conductive sheet, shaping the conductive sheet into at least two opposing longitudinal strips and a plurality of interposing strips, masking lateral sides and a center of the plurality of interposing strips, covering the exposed surface with a conductor and severing the conductive sheet at least along center mask. The plurality of interposing strips are preferably flexible and configurable into desired shapes for potential future attachment to an integrated circuit.Type: GrantFiled: November 5, 2007Date of Patent: June 12, 2012Assignee: General Dynamics Advanced Information Systems, Inc.Inventor: Deepak K. Pai
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Patent number: 8028403Abstract: The present invention provides a number of techniques for laminating and interconnecting multiple substrates to form a multilayer package or other circuit component. A solder bump may be formed on the conductive pad of at least one of two or more substrates. The solder bump preferably is formed from an application of solder paste to the conductive pad(s). Adhesive films may be positioned between the surfaces of the substrates having the conductive pads, where the adhesive films include apertures located substantially over the conductive pads such that the conductive pads and/or solder bumps confront each other through the aperture. The two or more substrates then may be pressed together to mechanically bond the two or more substrates via the adhesive films. The solder bump(s) may be reflowed during or after the lamination to create a solder segment that provides an electrical connection between the conductive pads through the aperture in the adhesive films.Type: GrantFiled: February 13, 2009Date of Patent: October 4, 2011Assignee: General Dynamics Advanced Information Systems, Inc.Inventors: Deepak K. Pai, Ronald R. Denny
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Publication number: 20110157855Abstract: A method is provided for connecting an integrated circuit to a surface of a printed wiring board. The integrated circuit includes lead contacts and leadless contact pads. A first solder paste is applied to the leadless contact pads of the integrated circuit, and preformed conductive pieces are placed on the first solder paste. The preformed conductive pieces are slugs that have, for example, a cylindrical shape or a rectangular cross-section. The preformed conductive pieces are heated and brought into electrical contact with the leadless contact pads. The lead contacts are formed into gull wings. The bases of the preformed conductive pieces are generally aligned in a plane, and the bases of the gull wings are substantially coplanar with the plane such that they collectively generally define a contact plane.Type: ApplicationFiled: March 8, 2011Publication date: June 30, 2011Applicant: GENERAL DYNAMICS ADVANCED INFORMATION SYSTEMSInventor: Deepak K. Pai
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Publication number: 20110101075Abstract: A method for preparing an integrated circuit for connection to a surface, the integrated circuit including lead contacts and leadless contacts, is provided. The method includes providing the integrated circuit, applying a first solder paste to the leadless contacts, forming solder balls on the applied solder paste, heating the solder balls, thereby removing at least a portion of the first solder paste and bringing the solder balls into electrical contact with the leadless contacts, the base of the solder balls being generally aligned in a plane, and bending the lead contacts into gull wings, with the base of the gull wings being substantially coplanar with the plane. The base of the gull wings and the base of the at least one of the solder balls collectively generally define a contact plane for potential future contact with the surface.Type: ApplicationFiled: January 10, 2011Publication date: May 5, 2011Applicant: General Dynamics Advanced Information SystemsInventor: Deepak K. Pai
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Patent number: 7892441Abstract: A method of manufacturing an interposer is provided, including the steps of providing a sheet with a copper layer and polyimide layer, laser drilling holes in the polyimide layer down to the copper layer, filling the holes with copper and extending the copper above the polyimide layer to define caps, removing portions of the copper layer to form conductive pads, and filling gaps between the conductive pads with an insulator, wherein individual conductive pads are in electrical contact with corresponding individual caps.Type: GrantFiled: June 1, 2007Date of Patent: February 22, 2011Assignee: General Dynamics Advanced Information Systems, Inc.Inventor: Deepak K. Pai
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Patent number: 7818879Abstract: A system for connecting circuit boards is provided. A plurality of overlapping spaced apart circuit boards have a plurality of conductive pins passing through holes in the circuit boards. A connector includes a flexible sheet insulator and a plurality of conductive surfaces separated and supported by the flexible insulator. At least one of the conductive surfaces has a hole there through and a bent compliant lead extending there from. The hole engages one of the pins, and the complaint lead connects to one of the circuit boards.Type: GrantFiled: March 13, 2009Date of Patent: October 26, 2010Assignee: General Dynamics Advanced Information Systems, Inc.Inventor: Deepak K. Pai
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Publication number: 20100175248Abstract: The present invention relates to a compliant leaded interposer for resiliently attaching and electrically connecting a ball grid array package to a circuit board. The interposer may include a substrate, a plurality of pads, and a plurality of pins. The plurality of pads may be positioned substantially on the top surface of the substrate and arranged in a predetermined pattern substantially corresponding to the solder ball pattern on the ball grid array package. The plurality of pins may be positioned substantially perpendicular to the substrate and may extend through the substrate and the plurality of pads. The interposer may be configured to attach the ball grid array package to the circuit board such that each of the solder balls on the ball grid array package contacts at least a portion the plurality of pins and at least a portion of the plurality of pads and such that the each of the plurality of pins also connects to a contact on the circuit board.Type: ApplicationFiled: March 22, 2010Publication date: July 15, 2010Applicant: General Dynamics AdvancedInventor: Deepak K. Pai
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Patent number: 7684205Abstract: The present invention relates to a compliant leaded interposer for resiliently attaching and electrically connecting a ball grid array package to a circuit board. The interposer may include a substrate, a plurality of pads, and a plurality of pins. The plurality of pads may be positioned substantially on the top surface of the substrate and arranged in a predetermined pattern substantially corresponding to the solder ball pattern on the ball grid array package. The plurality of pins may be positioned substantially perpendicular to the substrate and may extend through the substrate and the plurality of pads. The interposer may be configured to attach the ball grid array package to the circuit board such that each of the solder balls on the ball grid array package contacts at least a portion the plurality of pins and at least a portion of the plurality of pads and such that the each of the plurality of pins also connects to a contact on the circuit board.Type: GrantFiled: February 22, 2006Date of Patent: March 23, 2010Assignee: General Dynamics Advanced Information Systems, Inc.Inventor: Deepak K. Pai
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Patent number: 7614341Abstract: The present invention relates to a segmented squeegee for depositing a medium onto a surface, such as depositing solder paste onto a printed wiring board. The segmented squeegee may include a plurality of independent squeegee segments or elements, a support structure and a plurality of independent connections or linkages connecting the squeegee segments to the support structure. The segmented squeegee may be used in connection with a conventional stencil such that the independent linkages and the squeegee segments may be structured and arranged to maintain substantial contact between the stencil and the printed wiring board.Type: GrantFiled: March 10, 2005Date of Patent: November 10, 2009Assignee: General Dynamics Advanced Information Systems, Inc.Inventors: Deepak K. Pai, Scott P. Lichtenauer
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Publication number: 20090250506Abstract: A method for preparing an integrated circuit for connection to a surface, the integrated circuit including lead contacts and leadless contacts, is provided. The method includes providing the integrated circuit, applying a first solder paste to the leadless contacts, forming solder balls on the applied solder paste, heating the solder balls, thereby removing at least a portion of the first solder paste and bringing the solder balls into electrical contact with the leadless contacts, the base of the solder balls being generally aligned in a plane, and bending the lead contacts into gull wings, with the base of the gull wings being substantially coplanar with the plane. The base of the gull wings and the base of the at least one of the solder balls collectively generally define a contact plane for potential future contact with the surface.Type: ApplicationFiled: February 24, 2009Publication date: October 8, 2009Applicant: General Dynamics Advanced Information SystemsInventor: Deepak K. Pai
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Publication number: 20090151158Abstract: The present invention provides a number of techniques for laminating and interconnecting multiple substrates to form a multilayer package or other circuit component. A solder bump may be formed on the conductive pad of at least one of two or more substrates. The solder bump preferably is formed from an application of solder paste to the conductive pad(s). Adhesive films may be positioned between the surfaces of the substrates having the conductive pads, where the adhesive films include apertures located substantially over the conductive pads such that the conductive pads and/or solder bumps confront each other through the aperture. The two or more substrates then may be pressed together to mechanically bond the two or more substrates via the adhesive films. The solder bump(s) may be reflowed during or after the lamination to create a solder segment that provides an electrical connection between the conductive pads through the aperture in the adhesive films.Type: ApplicationFiled: February 13, 2009Publication date: June 18, 2009Inventors: Deepak K. Pai, Ronald R. Denny
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Patent number: 7490402Abstract: The present invention provides a number of techniques for laminating and interconnecting multiple substrates to form a multilayer package or other circuit component. A solder bump may be formed on the conductive pad of at least one of two or more substrates. The solder bump preferably is formed from an application of solder paste to the conductive pad(s). Adhesive films may be positioned between the surfaces of the substrates having the conductive pads, where the adhesive films include apertures located substantially over the conductive pads such that the conductive pads and/or solder bumps confront each other through the aperture. The two or more substrates then may be pressed together to mechanically bond the two or more substrates via the adhesive films. The solder bump(s) may be reflowed during or after the lamination to create a solder segment that provides an electrical connection between the conductive pads through the aperture in the adhesive films.Type: GrantFiled: September 25, 2007Date of Patent: February 17, 2009Assignee: General Dynamics Advanced Information Systems, Inc.Inventors: Deepak K. Pai, Ronald R. Denny
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Publication number: 20080296253Abstract: A method of manufacturing an interposer is provided, including the steps of providing a sheet with a copper layer and polyimide layer, laser drilling holes in the polyimide layer down to the copper layer, filling the holes with copper and extending the copper above the polyimide layer to define caps, removing portions of the copper layer to form conductive pads, and filling gaps between the conductive pads with an insulator, wherein individual conductive pads are in electrical contact with corresponding individual caps.Type: ApplicationFiled: June 1, 2007Publication date: December 4, 2008Inventor: Deepak K. Pai
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Patent number: 7282787Abstract: The present invention is for laminated and interconnected multiple substrates forming a multilayer package or other circuit component. A solder bump may be situated on the conductive pad of at least one of two or more substrates. The solder bump preferably is formed from an application of solder paste to the conductive pad(s). Adhesive films may be positioned between the surfaces of the substrates having the conductive pads, where the adhesive films include apertures located substantially over the conductive pads such that the conductive pads and/or solder bumps confront each other through the aperture. The two or more substrates pressed together via the adhesive films are mechanically bonded. The solder bump(s) may be reflowed during or after the lamination to create a solder segment that provides an electrical connection between the conductive pads through the aperture in the adhesive films.Type: GrantFiled: April 21, 2004Date of Patent: October 16, 2007Assignee: General Dynamics Advanced Information Systems, Inc.Inventors: Deepak K. Pai, Ronald R. Denny
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Publication number: 20070193772Abstract: The present invention relates to a compliant leaded interposer for resiliently attaching and electrically connecting a ball grid array package to a circuit board. The interposer may include a substrate, a plurality of pads, and a plurality of pins. The plurality of pads may be positioned substantially on the top surface of the substrate and arranged in a predetermined pattern substantially corresponding to the solder ball pattern on the ball grid array package. The plurality of pins may be positioned substantially perpendicular to the substrate and may extend through the substrate and the plurality of pads. The interposer may be configured to attach the ball grid array package to the circuit board such that each of the solder balls on the ball grid array package contacts at least a portion the plurality of pins and at least a portion of the plurality of pads and such that the each of the plurality of pins also connects to a contact on the circuit board.Type: ApplicationFiled: February 22, 2006Publication date: August 23, 2007Applicant: General Dynamics Advanced Information Systems, Inc.Inventor: Deepak K. Pai
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Patent number: 6856008Abstract: The present invention provides a number of techniques for laminating and interconnecting multiple high-layer-count (HLC) substrates to form a multilayer package or other circuit component. A solder bump may be formed on the conductive pad of at least one of two HLC substrates. The solder bump preferably is formed from an application of solder paste to the conductive pad(s). An adhesive film may be positioned between the surfaces of the HLC substrates having the conductive pads, where the adhesive film includes an aperture located substantially over the conductive pads such that the conductive pads and/or solder bumps confront each other through the aperture. The HLC substrates then may be pressed together to mechanically bond the two substrates via the adhesive. The solder bump(s) may be reflowed during or after the lamination to create a solder segment that provides an electrical connection between the two conductive pads through the aperture in the adhesive film.Type: GrantFiled: August 15, 2003Date of Patent: February 15, 2005Assignee: General Dynamics Advanced Information Systems, Inc.Inventors: Deepak K. Pai, Ronald R. Denny
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Patent number: 6830177Abstract: The present invention comprises cost-effectively manufactured, electrically conductive and mechanically compliant micro-leads and a method of utilizing these compliant micro-leads to interconnect area grid array chip scale packages (“CSPs”) to printed wiring boards (“PWBs”). The preferred method includes orienting a plurality of conductive compliant micro-leads, secured to one another in parallel with tie bars and tooling, to align with a corresponding pattern of conductive pads located along the surface of an area grid array CSP. The compliant micro-leads are electrically connected and mechanically secured to the corresponding connecting surfaces of the area grid array CSP. Next, the securing tie bars and the tooling are removed. The opposite ends of the conductive compliant micro-leads are then oriented to align with a corresponding pattern of conductive surface pads on a PWB.Type: GrantFiled: September 10, 2002Date of Patent: December 14, 2004Assignee: General Dynamics Information Systems, Inc.Inventor: Deepak K. Pai
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Publication number: 20040246688Abstract: The present invention provides a number of techniques for laminating and interconnecting multiple substrates to form a multilayer package or other circuit component. A solder bump may be formed on the conductive pad of at least one of two or more substrates. The solder bump preferably is formed from an application of solder paste to the conductive pad(s). Adhesive films may be positioned between the surfaces of the substrates having the conductive pads, where the adhesive films include apertures located substantially over the conductive pads such that the conductive pads and/or solder bumps confront each other through the aperture. The two or more substrates then may be pressed together to mechanically bond the two or more substrates via the adhesive films. The solder bump(s) may be reflowed during or after the lamination to create a solder segment that provides an electrical connection between the conductive pads through the aperture in the adhesive films.Type: ApplicationFiled: April 21, 2004Publication date: December 9, 2004Applicant: General Dynamics Advanced Information Systems, Inc.Inventors: Deepak K. Pai, Ronald R. Denny