Patents by Inventor Deepak M. Rangaraj

Deepak M. Rangaraj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method, apparatus and system for configuring a protocol stack of an integrated circuit chip
    Patent number: 10282341
    Abstract: Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: May 7, 2019
    Assignee: Intel Corporation
    Inventors: Bryan L. Spry, Marcus W. Song, Deepak M. Rangaraj, Avinash N. Ananthakrishnan, Robert J. Hayes, Aimee D. Wood, Adam E. Letendre, Brent R. Boswell
  • METHOD, APPARATUS AND SYSTEM FOR CONFIGURING A PROTOCOL STACK OF AN INTEGRATED CIRCUIT CHIP
    Publication number: 20180210857
    Abstract: Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information.
    Type: Application
    Filed: August 8, 2017
    Publication date: July 26, 2018
    Inventors: Bryan L. Spry, Marcus W. Song, Deepak M. Rangaraj, Avinash N. Ananthakrishnan, Robert J. Hayes, Aimee D. Wood, Brent R. Boswell
  • Method, apparatus and system for configuring a protocol stack of an integrated circuit chip
    Patent number: 9734116
    Abstract: Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Bryan L. Spry, Marcus W. Song, Deepak M. Rangaraj, Avinash N. Ananthakrishnan, Robert J. Hayes, Aimee D. Wood, Adam E. Letendre, Brent R. Boswell
  • METHOD, APPARATUS AND SYSTEM FOR CONFIGURING A PROTOCOL STACK OF AN INTEGRATED CIRCUIT CHIP
    Publication number: 20150269108
    Abstract: Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information.
    Type: Application
    Filed: March 13, 2015
    Publication date: September 24, 2015
    Inventors: Bryan L. Spry, Marcus W. Song, Deepak M. Rangaraj, Avinash N. Ananthakrishnan, Robert J. Hayes, Aimee D. Wood, Adam E. Letendre, Brent R. Boswell