Patents by Inventor Deepak N
Deepak N has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11954783Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The graphics subsystem may include a first graphics engine to process a graphics workload, and a second graphics engine to offload at least a portion of the graphics workload from the first graphics engine. The second graphics engine may include a low precision compute engine. The system may further include a wearable display housing the second graphics engine. Other embodiments are disclosed and claimed.Type: GrantFiled: December 29, 2021Date of Patent: April 9, 2024Assignee: Intel CorporationInventors: Atsuo Kuwahara, Deepak S. Vembar, Chandrasekaran Sakthivel, Radhakrishnan Venkataraman, Brent E. Insko, Anupreet S. Kalra, Hugues Labbe, Abhishek R. Appu, Ankur N. Shah, Joydeep Ray, Elmoustapha Ould-Ahmed-Vall, Prasoonkumar Surti, Murali Ramadoss
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Patent number: 11956310Abstract: A method and system for providing information management of data from hosted services receives information management policies for a hosted account of a hosted service, requests data associated with the hosted account from the hosted service, receives data associated with the hosted account from the hosted service, and provides a preview version of the received data to a computing device. In some examples, the system indexes the received data to associate the received data with a user of an information management system, and/or provides index information related to the received data to the computing device.Type: GrantFiled: April 5, 2021Date of Patent: April 9, 2024Assignee: Commvault Systems, Inc.Inventors: Manoj Kumar Vijayan, Ho-Chi Chen, Deepak Raghunath Attarde, Hetalkumar N. Joshi
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Publication number: 20220151318Abstract: An aftermarket device for attachment to a facial mask includes a strip, front fingers and back fingers. The front fingers fold over the strip for retaining an upper edge of a face mask. The strip is configurable to conform to a user's cheeks and around ridge of the user's nose for use. The back fingers are configurable to or otherwise extend along either side of the ridge of the user's nose when in use. The device conforms the facial mask to the user's face in vicinity of the upper edge of the mask, along the cheeks and the user's nose. The device lifts the facial mask from contact with at least a portion of the user's nose and from contact to the mouth.Type: ApplicationFiled: February 3, 2022Publication date: May 19, 2022Applicant: Vanguard Masks, LLCInventors: Nilesh N. Kotecha, Deepak N. Kotecha
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Publication number: 20220117330Abstract: An aftermarket device for attachment to a facial mask includes a support layer and an adhesive segment. The support layer is sized to fold over and under a central portion of an upper edge of the facial mask and to extend laterally from centrally along the upper edge of the mask. The adhesive segment is connected to the support layer configured to connect to the facial mask. The device supports the facial mask during wear to conform the upper edge of the mask to a wearer's face along the nose and the cheeks under the eyes. The device extends the facial mask along bridge of the wearer's nose. The device may assist in comfort of mask wear, avoidance of irritation of the mask against skin, and limit frequent hand adjustment of the mask during wear.Type: ApplicationFiled: October 15, 2020Publication date: April 21, 2022Applicant: Vanguard Masks, LLCInventors: Nilesh N. Kotecha, Deepak N. Kotecha
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Publication number: 20200400390Abstract: An apparatus (e.g., tube sheet) includes a plate piece, a sleeve piece, and a tube piece. The plate piece defines a hole. The sleeve piece has first and second ends; the second end is shaped to fit through the hole for attachment of the sleeve piece to the plate piece. The tube piece also has first and second ends. Inner and outer cross-sectional geometries of the tube piece and the sleeve piece (e.g., in the case of round tubes, inner and outer diameters) are shaped for the first end of the tube piece to fit in the first end of the sleeve piece and to form a continuous interior fluid flow path from the second end of the tube piece through the plate piece when the sleeve piece is disposed in the hole and attached to the plate piece and the tube piece is disposed in the sleeve piece.Type: ApplicationFiled: July 8, 2020Publication date: December 24, 2020Inventors: John Patrick Dowell, Eric David Peters, Hafiz Hassan Eisa, Deepak N.
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Publication number: 20180142966Abstract: An apparatus (e.g., tube sheet) includes a plate piece, a sleeve piece, and a tube piece. The plate piece defines a hole. The sleeve piece has first and second ends; the second end is shaped to fit through the hole for attachment of the sleeve piece to the plate piece. The tube piece also has first and second ends. Inner and outer cross-sectional geometries of the tube piece and the sleeve piece (e.g., in the case of round tubes, inner and outer diameters) are shaped for the first end of the tube piece to fit in the first end of the sleeve piece and to form a continuous interior fluid flow path from the second end of the tube piece through the plate piece when the sleeve piece is disposed in the hole and attached to the plate piece and the tube piece is disposed in the sleeve piece.Type: ApplicationFiled: November 22, 2017Publication date: May 24, 2018Inventors: John Patrick DOWELL, Eric David PETERS, Hafiz Hassan EISA, Deepak N
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Publication number: 20090267329Abstract: A cover panel for the air bag in an automotive vehicle with a pre-weakened tear seam being formed by a series of voids formed in a predetermined repeat pattern of varying depths. The voids are formed by ablating the cover panel base substrate from its under side at varying depths to weaken both the base substrate and an outer finish layer.Type: ApplicationFiled: April 29, 2008Publication date: October 29, 2009Inventors: Raymond E. Kalisz, Kenneth J. Kwasnik, Deepak N. Patel
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Patent number: 7129008Abstract: New photosensitive acrylic material compositions for fabrication of holographic recording materials (HRMs) are provided. These compositions are comprised of polymerizable acrylic monomers and light absorbing dyes, and when polymerized they are thermally stable, light sensitive, hard and inert to common chemicals. Methods of fabricating HRMs with symmetric concentration distribution of the dye are also provided.Type: GrantFiled: June 12, 2003Date of Patent: October 31, 2006Assignee: Laser Photonics Technology Inc.Inventors: Ryszard Burzynski, Deepak N. Kumar, Saswati Ghosal, Dale R. Tyczka
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Patent number: 6811470Abstract: Methods and compositions are provided for planarizing a substrate surface with reduced or minimal defects in surface topography. In one aspect, a method is provided for processing a substrate including positioning a substrate comprising at least first dielectric material and second dielectric material disposed thereon in a polishing apparatus, polishing the substrate with a first polishing composition having a first selectivity, and polishing the substrate with a second polishing composition having a second selectivity greater than the first selectivity.Type: GrantFiled: July 12, 2002Date of Patent: November 2, 2004Assignee: Applied Materials Inc.Inventors: Benjamin A. Bonner, Anand N. Iyer, Deepak N. Kumar, Thomas H. Osterheld, Wei-Yung Hsu, Yong-Sik R. Kim, Christopher W. Smith, Huanbo Zhang
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Publication number: 20040033423Abstract: New photosensitive acrylic material compositions for fabrication of holographic recording materials (HRMS) are provided. These compositions are comprised of polymerizable acrylic monomers and light absorbing dyes, and when polymerized they are thermally stable, light sensitive, hard and inert to common chemicals. Methods of fabricating HRMs with symmetric concentration distribution of the dye are also provided.Type: ApplicationFiled: June 12, 2003Publication date: February 19, 2004Inventors: Ryszard Burzynski, Deepak N. Kumar, Saswati Ghosal, Dale R. Tyczka
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Publication number: 20030036339Abstract: Methods and compositions are provided for planarizing a substrate surface with reduced or minimal defects in surface topography. In one aspect, a method is provided for processing a substrate including positioning a substrate comprising at least first dielectric material and second dielectric material disposed thereon in a polishing apparatus, polishing the substrate with a first polishing composition having a first selectivity, and polishing the substrate with a second polishing composition having a second selectivity greater than the first selectivity.Type: ApplicationFiled: July 12, 2002Publication date: February 20, 2003Applicant: Applied Materials, Inc.Inventors: Benjamin A. Bonner, Anand N. Iyer, Deepak N. Kumar, Thomas H. Osterheld, Wei-Yung Hsu, Yong-Sik R. Kim, Christopher W. Smith, Huanbo Zhang
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Publication number: 20020068225Abstract: New photosensitive acrylic material compositions for fabrication of holographic recording materials (HRMs) are provided. These compositions are comprised of polymerizable acrylic monomers and light absorbing dyes, and when polymerized they are thermally stable, light sensitive, hard and inert to common chemicals. Methods of fabricating HRMs with symmetric concentration distribution of the dye are also provided.Type: ApplicationFiled: November 16, 2001Publication date: June 6, 2002Inventors: Ryszard Burzynski, Deepak N. Kumar, Saswati Ghosal, Dale R. Tyczka
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Patent number: 6344297Abstract: New photosensitive acrylic material compositions for fabrication of holographic recording materials (HRMs) are provided. These compositions are comprised of polymerizable acrylic monomers and light absorbing dyes, and when polymerized they are thermally stable, light sensitive, hard and inert to common chemicals. Methods of fabricating HRMs with symmetric concentration distribution of the dye are also provided.Type: GrantFiled: October 12, 1999Date of Patent: February 5, 2002Assignee: Laser Photonics Technology Inc.Inventors: Ryszard Burzynski, Deepak N. Kumar, Saswati Ghosal, Dale R. Tyczka
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Patent number: 5987553Abstract: A computer system includes a motherboard to which a selected one of various processor boards can be coupled via an adaptor. The boards include a CPU and a heat transfer member. The adaptor includes core logic such as a Northbridge module and power control circuitry. The adaptor is pin connectable to the motherboard and the various processor boards are each pin connectable to the adaptor. Alternatively, the adaptor and processor boards can be replaced with a processor module including features of the processor boards and the adaptor. The processor module is also pin connectable to the motherboard at the same connection used by the adaptor.Type: GrantFiled: September 22, 1997Date of Patent: November 16, 1999Assignee: Dell Computer CorporationInventors: Deepak N. Swamy, Andrew W. Moore
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Patent number: 5576519Abstract: An interconnect sheet for connecting multiple layers of a circuit board for the manufacture of high interconnect density PWBs. The interconnect sheet preferably comprises an area array grid of 0.003 inch solder columns having a 0.006 inch pitch. The interconnect sheet is preferably used to attach two or more multi-layer boards by placing one sheet at every interconnect surface. This interconnect mechanism has an advantage of redundancy of contact and therefore lower susceptibility to failure than other methods. The interconnect sheet of the present invention also offers a large tolerance for registration error without shorting adjacent pads. The preferred method of fabrication of the interconnect sheet begins with creating equally spaced holes through a 0.5 ounce double sided laminate comprising a dielectric sheet and copper plates on either side of the dielectric. These holes are filled with solder paste and the sheet undergoes a baking process to shrink the paste.Type: GrantFiled: March 23, 1995Date of Patent: November 19, 1996Assignee: Dell U.S.A., L.P.Inventor: Deepak N. Swamy
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Patent number: 5567295Abstract: An inexpensive method for fabricating a staggered edge connector for a circuit board. The method is cost effective and includes numerous advantages over the prior art, including allowing more area for signal routing and removing the problems associated with capacitive stubs on edge connector traces associated with prior art designs. The method begins with creating a staggered plurality of blades or fingers. A plating bus is formed on these staggered blades by connecting a gold plating bus to one of the contact pads and then shorting together or connecting the signal lines via a shorting bus. The shorting bus is placed flush with the innermost edge of the edge connector well outside of the actual wipe area of the connectors. The board then undergoes a standard semi-additive process, as well as a final etch and subsequent gold plating. The shorting bar is then drilled out.Type: GrantFiled: January 11, 1994Date of Patent: October 22, 1996Assignee: Dell USA L.P.Inventors: Deepak N. Swamy, Victor K. Pecone
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Patent number: 5456004Abstract: An interconnect sheet for connecting multiple layers of a circuit board for the manufacture of high interconnect density PWBs. The interconnect sheet preferably comprises an area array grid of 0.003 inch solder columns having a 0.006 inch pitch. The interconnect sheet is preferably used to attach two or more multi-layer boards by placing one sheet at every interconnect surface. This interconnect mechanism has an advantage of redundancy of contact and therefore lower susceptibility to failure than other methods. The interconnect sheet of the present invention also offers a large tolerance for registration error without shorting adjacent pads. The preferred method of fabrication of the interconnect sheet begins with creating equally spaced holes through a 0.5 ounce double sided laminate comprising a dielectric sheet and copper plates on either side of the dielectric. These holes are filled with solder paste and the sheet undergoes a baking process to shrink the paste.Type: GrantFiled: January 4, 1994Date of Patent: October 10, 1995Assignee: Dell USA, L.P.Inventor: Deepak N. Swamy
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Patent number: 5424492Abstract: An optimal routing methodology for routing high I/O density packages which minimizes the number of PCB layers required. One feature of this routing methodology comprises treating respective I/O that are routed at the top layer of the package as surface mount technology (SMT) pads without dropping vias within the BGA grid, as is commonplace in the industry. This facilitates the use of fewer escapes and allows for more efficient use of the available space. Signal lines on the top layer of the package which must be routed to other layers of the PCB are connected to vias outside of the area of local high signal density on the printed circuit board. The placement of vias outside the area of local high density, i.e., in a depopulated area, reduces the number of layers necessary in the PCB to properly route the signals. This placement also facilitates the use of filtering capacitors to meet EMI requirements. In addition, all voltage pins are placed on the innermost or outermost grids and have clearanced vias.Type: GrantFiled: January 6, 1994Date of Patent: June 13, 1995Assignee: Dell USA, L.P.Inventors: Robert B. Petty, Michael D. Ohlinger, Deepak N. Swamy, Joseph Mallory
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Patent number: 5392980Abstract: A rework process for ball grid array (BGA) packages which allows for reuse of devices that have been removed for lack of integrity of solder interconnections. The process uses a rework tool which comprises a plate including one or more depressions corresponding to the contours of inverted BGA packages. A BGA package to be reworked is placed in a respective depression with what remains of the original solder ball grid facing upward. The residual solder balls are wicked away, thus leaving the BGA package with the pads that the solder balls were attached to being exposed. A stencil with BGA patterns punched into it is then placed over the rework tool and solder paste is screened onto the rework tool so that the solder is deposited on the BGA pads via the openings in the stencil. The entire fixture is then subjected to a reflow process to cause the solder to ball up during this process.Type: GrantFiled: December 29, 1993Date of Patent: February 28, 1995Assignee: Dell USA, L.P.Inventors: Deepak N. Swamy, Scott Estes, James Bell
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Patent number: 5276955Abstract: A method and apparatus for manufacturing large area multilayer interconnects for electronic substrates and circuit boards uses high density area array interconnections that are created by solid state diffusion. Two or more pretested subsections are electrically and mechanically joined together to simultaneously form a multilayer substrate without employing a flow-type connection where the conductive interconnect material is entirely in a liquid phase at some point during the joining process. Each substrate is comprised of a planar dielectric substrate having a plurality of conductive layers. On at least one surface of the substrate a conductive pad lay is formed having a plurality of interconnect pads. The interconnect pads are positioned at a uniform height above the surface of the dielectric substrate and include a base metal layer, a top metal layer with at least one of the conductive pad layers have a donor metal disposed on top of the top metal layer.Type: GrantFiled: April 14, 1992Date of Patent: January 11, 1994Assignee: Supercomputer Systems Limited PartnershipInventors: David B. Noddin, Robin E. Gorrell, William G. Petefish, Kevin L. Stumpe, Boydd Piper, Deepak N. Swamy, Jimmy Leong, Michael R. Leaf