Patents by Inventor Deepti Saini

Deepti Saini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Transistor body bias control circuit for SRAM cells
    Patent number: 10685703
    Abstract: A semiconductor memory circuit includes a SRAM cell and a bias control circuit for biasing the SRAM cell. The SRAM cell includes pull-up, pull-down, and pass-gate transistors. The bias control circuit is connected to body terminals of the pull-down and pass-gate transistors for providing a bias voltage. The bias control circuit controls threshold voltages of the pull-down and pass-gate transistors by way of the bias voltage. The bias voltage, which is temperature dependent, is generated based on junction leakages at the body terminals of the pull-down and pass-gate transistors. The use of a temperature-dependent bias voltage to bias the body terminals of the pull-down and pass-gate transistors ensures that the write margin and the static noise margin (SNM) of the SRAM cell are relatively constant and above acceptable levels over a defined temperature range.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: June 16, 2020
    Assignee: NXP B.V.
    Inventors: Jainendra Singh, Sushikha Jain, Deepti Saini, Jwalant Kumar Mishra, Patrick Van de Steeg
  • TRANSISTOR BODY BIAS CONTROL CIRCUIT FOR SRAM CELLS
    Publication number: 20200082876
    Abstract: A semiconductor memory circuit includes a SRAM cell and a bias control circuit for biasing the SRAM cell. The SRAM cell includes pull-up, pull-down, and pass-gate transistors. The bias control circuit is connected to body terminals of the pull-down and pass-gate transistors for providing a bias voltage. The bias control circuit controls threshold voltages of the pull-down and pass-gate transistors by way of the bias voltage. The bias voltage, which is temperature dependent, is generated based on junction leakages at the body terminals of the pull-down and pass-gate transistors. The use of a temperature-dependent bias voltage to bias the body terminals of the pull-down and pass-gate transistors ensures that the write margin and the static noise margin (SNM) of the SRAM cell are relatively constant and above acceptable levels over a defined temperature range.
    Type: Application
    Filed: September 12, 2018
    Publication date: March 12, 2020
    Inventors: Jainendra Singh, Sushikha Jain, Deepti Saini, Jwalant Kumar Mishra, Patrick Van de Steeg