Patents by Inventor Dejia Huang
Dejia Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230335194Abstract: A memory includes wordline (WL) layers and a controller coupled to the WL layers. The controller is configured to apply at least one verify voltage to a first WL layer of the WL layers during a verify phase, and apply a first pass voltage to a second WL layer of the WL layers during the verify phase. A first memory cell of the first WL layer is programmed before a second memory cell of the second WL layer. The first pass voltage is higher than a threshold voltage of a memory cell in a lowest programming state.Type: ApplicationFiled: June 16, 2023Publication date: October 19, 2023Inventors: Hongtao Liu, Song Min Jiang, Dejia Huang, Ying Huang, Wenzhe Wei
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Patent number: 11727990Abstract: An operation method for a 3D NAND flash including a plurality of wordline (WL) layers. The operation method includes: writing data into a WLn layer of the plurality of WL layers according to a writing sequence from a first end of the plurality of WL layers to a second end of the plurality of WL layers in a write operation, wherein the WLn layer is a selected WL layer; and applying a first pass voltage on a first WL layer of the plurality of WL layers and applying a second pass voltage on a second WL layer of the plurality of WL layers during a verify phase; wherein the operation method is operated without a pre-pulse phase during or before the verify phase.Type: GrantFiled: May 23, 2022Date of Patent: August 15, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Hongtao Liu, Song Min Jiang, Dejia Huang, Ying Huang, Wenzhe Wei
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Publication number: 20230148136Abstract: The present disclosure provides a configuration method and a reading method for a 3D memory, a 3D memory and system. The configuration method includes: writing test data into a plurality of selected memory cells corresponding to a selected word line in one of a plurality of memory blocks of the memory device; determining threshold voltages of the plurality of selected memory cells; and obtaining a relationship table indicating a corresponding relationship between a number of a subset of the selected memory cells that have threshold voltages lower than a preset voltage and a pass voltage required for performing a read operation on the one memory block.Type: ApplicationFiled: December 28, 2022Publication date: May 11, 2023Inventors: Hongtao Liu, Songmin Jiang, Dejia Huang
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Publication number: 20230132781Abstract: In certain aspects, a memory device includes memory strings each including a drain select gate (DSG) transistor and memory cells, and a peripheral circuit coupled to the memory strings. The peripheral circuit is configured to, in a program/verify cycle, program a target memory cell of the memory cells in a select memory string of the memory strings, and after programming the target memory cell, verify the target memory cell using one or more verify voltages including an initial verify voltage. The peripheral circuit is also configured to compare the initial verify voltage with a threshold verify voltage so as to obtain a comparing result, and control, at least based on the comparing result, the DSG transistor in an unselect memory string of the memory strings between programming and verifying the targe memory cell.Type: ApplicationFiled: November 18, 2021Publication date: May 4, 2023Inventors: Hongtao Liu, Dejia Huang, Wenzhe Wei, Ying Huang
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Publication number: 20220351779Abstract: A programming method for a memory device is disclosed. The programming method comprises moving a plurality of first charge carriers at a shallow energy level to a channel in a substrate layer before a programming operation for a first word line, wherein the plurality of first charge carriers at the shallow energy level correspond to a memory cell to be programmed.Type: ApplicationFiled: July 18, 2022Publication date: November 3, 2022Inventors: Hongtao Liu, Ying Huang, Wenzhe Wei, Song Min Jiang, Dejia Huang, Wen Qiang Chen
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Publication number: 20220284960Abstract: An operation method for a 3D NAND flash including a plurality of wordline (WL) layers. The operation method includes: writing data into a WLn layer of the plurality of WL layers according to a writing sequence from a first end of the plurality of WL layers to a second end of the plurality of WL layers in a write operation, wherein the WLn layer is a selected WL layer; and applying a first pass voltage on a first WL layer of the plurality of WL layers and applying a second pass voltage on a second WL layer of the plurality of WL layers during a verify phase; wherein the operation method is operated without a pre-pulse phase during or before the verify phase.Type: ApplicationFiled: May 23, 2022Publication date: September 8, 2022Inventors: Hongtao Liu, Song Min Jiang, Dejia Huang, Ying Huang, Wenzhe Wei
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Patent number: 11423987Abstract: A programming method for a memory device is disclosed. The programming method comprises moving a plurality of first charge carriers at a shallow energy level to a channel in a substrate layer before a fine programming operation for a first word line, wherein the plurality of first charge carriers at the shallow energy level correspond to a memory cell to be programmed.Type: GrantFiled: June 1, 2020Date of Patent: August 23, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Hongtao Liu, Ying Huang, Wenzhe Wei, Song Min Jiang, Dejia Huang, Wen Qiang Chen
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Patent number: 11342023Abstract: An operation method for a 3D NAND flash includes writing data into a WLn layer of the plurality of wordline layers of an unselect bit line of the plurality of bit lines in a write operation; and applying a first pass voltage on at least a first WL layer of the plurality of wordline layers of the unselect bit line of the plurality of bit lines and applying a second pass voltage on at least a second WL layer of the plurality of wordline layers of the unselect bit line of the plurality of bit lines; wherein the operation method is operated when a pre-pulse phase is removed from a verify phase.Type: GrantFiled: March 11, 2021Date of Patent: May 24, 2022Assignee: Yangzte Memory Technologies., Ltd.Inventors: Hongtao Liu, Song Min Jiang, Dejia Huang, Ying Huang, Wenzhe Wei
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Patent number: 11257545Abstract: In a memory device which includes a plurality of memory cells, a top dummy storage region, a bottom dummy storage region, a plurality of word lines and a plurality of bit lines form in a substrate, a selected bit line among the plurality of bit lines, a channel region in the substrate and a source region in the substrate are pre-charged and a negative pre-pulse voltage is applied to the bottom dummy storage region during a first period. A selected memory cell among the plurality of memory cells is programmed during a second period subsequent to the first period, wherein the selected memory cell is coupled to the selected bit line and a selected word line among the plurality of word lines.Type: GrantFiled: February 26, 2021Date of Patent: February 22, 2022Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Wenzhe Wei, Hongtao Liu, Kaikai You, Da Li, Ying Huang, Yali Song, Dejia Huang
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Publication number: 20210366545Abstract: An operation method for a 3D NAND flash includes writing data into a WLn layer of the plurality of wordline layers of an unselect bit line of the plurality of bit lines in a write operation; and applying a first pass voltage on at least a first WL layer of the plurality of wordline layers of the unselect bit line of the plurality of bit lines and applying a second pass voltage on at least a second WL layer of the plurality of wordline layers of the unselect bit line of the plurality of bit lines; wherein the operation method is operated when a pre-pulse phase is removed from a verify phase.Type: ApplicationFiled: March 11, 2021Publication date: November 25, 2021Inventors: Hongtao Liu, Song Min Jiang, Dejia Huang, Ying Huang, Wenzhe Wei
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Patent number: 11177001Abstract: A programming method of an increment step pulse program (ISPP) for a three-dimension (3D) NAND flash includes programming a select wordline of an unselect bit line of the 3D NAND flash; performing a first verification process with at least a verification voltage on the select wordline; determining whether a first verification voltage of the first verification process for the select wordline is higher than a default voltage or not; and removing a pre-pulse phase of the ISPP when the first verification voltage is higher than the default voltage; wherein the first verification voltage is a following verification voltage of the first verification process.Type: GrantFiled: June 1, 2020Date of Patent: November 16, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Hongtao Liu, Dejia Huang, Wenzhe Wei, Ying Huang
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Publication number: 20210343344Abstract: A programming method for a memory device is disclosed. The programming method comprises moving a plurality of first charge carriers at a shallow energy level to a channel in a substrate layer before a fine programming operation for a first word line, wherein the plurality of first charge carriers at the shallow energy level correspond to a memory cell to be programmed.Type: ApplicationFiled: June 1, 2020Publication date: November 4, 2021Inventors: Hongtao Liu, Ying Huang, Wenzhe Wei, Song Min Jiang, Dejia Huang, Wen Qiang Chen
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Publication number: 20210327511Abstract: A programming method of an increment step pulse program (ISPP) for a three-dimension (3D) NAND flash includes programming a select wordline of an unselect bit line of the 3D NAND flash; performing a first verification process with at least a verification voltage on the select wordline; determining whether a first verification voltage of the first verification process for the select wordline is higher than a default voltage or not; and removing a pre-pulse phase of the ISPP when the first verification voltage is higher than the default voltage; wherein the first verification voltage is a following verification voltage of the first verification process.Type: ApplicationFiled: June 1, 2020Publication date: October 21, 2021Inventors: Hongtao Liu, Dejia Huang, Wenzhe Wei, Ying Huang
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Publication number: 20210183449Abstract: In a memory device which includes a plurality of memory cells, a top dummy storage region, a bottom dummy storage region, a plurality of word lines and a plurality of bit lines form in a substrate, a selected bit line among the plurality of bit lines, a channel region in the substrate and a source region in the substrate are pre-charged and a negative pre-pulse voltage is applied to the bottom dummy storage region during a first period. A selected memory cell among the plurality of memory cells is programmed during a second period subsequent to the first period, wherein the selected memory cell is coupled to the selected bit line and a selected word line among the plurality of word lines.Type: ApplicationFiled: February 26, 2021Publication date: June 17, 2021Inventors: Wenzhe Wei, Hongtao Liu, Kaikai You, Da Li, Ying Huang, Yali Song, Dejia Huang
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Patent number: 10998049Abstract: In a memory device which includes a plurality of memory cells, a top dummy storage region, a bottom dummy storage region, a plurality of word lines and a plurality of bit lines form in a substrate, a selected bit line among the plurality of bit lines, a channel region in the substrate and a source region in the substrate are pre-charged and a negative pre-pulse voltage is applied to the bottom dummy storage region during a first period. A selected memory cell among the plurality of memory cells is programmed during a second period subsequent to the first period, wherein the selected memory cell is coupled to the selected bit line and a selected word line among the plurality of word lines.Type: GrantFiled: December 5, 2019Date of Patent: May 4, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Wenzhe Wei, Hongtao Liu, Kaikai You, Da Li, Ying Huang, Yali Song, Dejia Huang
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Publication number: 20210125672Abstract: In a memory device which includes a plurality of memory cells, a top dummy storage region, a bottom dummy storage region, a plurality of word lines and a plurality of bit lines form in a substrate, a selected bit line among the plurality of bit lines, a channel region in the substrate and a source region in the substrate are pre-charged and a negative pre-pulse voltage is applied to the bottom dummy storage region during a first period. A selected memory cell among the plurality of memory cells is programmed during a second period subsequent to the first period, wherein the selected memory cell is coupled to the selected bit line and a selected word line among the plurality of word lines.Type: ApplicationFiled: December 5, 2019Publication date: April 29, 2021Inventors: Wenzhe Wei, Hongtao Liu, Kaikai You, Da Li, Ying Huang, Yali Song, Dejia Huang
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Patent number: 10978153Abstract: An operation method for a 3D NAND flash includes writing data into a WLn layer of the plurality of wordline layers of an unselect bit line of the plurality of bit lines in a write operation; and applying a first pass voltage on at least a first WL layer of the plurality of wordline layers of the unselect bit line of the plurality of bit lines and applying a second pass voltage on at least a second WL layer of the plurality of wordline layers of the unselect bit line of the plurality of bit lines; wherein the first pass voltage is lower than the second pass voltage to reduce a difference of channel potential between the WLn layer and the at least a first WL layer when a pre-pulse phase is removed from a verify phase.Type: GrantFiled: June 21, 2020Date of Patent: April 13, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Hongtao Liu, Song Min Jiang, Dejia Huang, Ying Huang, Wenzhe Wei