Abstract: The present invention discloses a cooperative scheduling method and system for a computing resource and a network resource of a container cloud platform. The method includes: obtaining a load value of a container in a physical machine of a data center; calculating a load margin of a current container; if the load margin of the current container is less than 0, generating a first container sequence; if the load margin of the current container is greater than 0, obtaining a load value of a next container managed by a current physical machine, calculating a load margin of the next container, and updating the calculated load margin of the next container to the load margin of the current container. According to the method and the system of the present invention, resource utilization can be effectively improved.

Abstract: Disclosed herein are embodiments of an apparatus and a method for generating a quadrature clock signal. In one aspect, the apparatus includes a first delay circuitry to delay a clock signal according to a first control signal to generate a first delayed clock signal. In one aspect, the apparatus includes a second delay circuitry to delay the clock signal according to a second control signal to generate a second delayed clock signal. In one aspect, the apparatus includes a delay controller forming a first feedback loop with the first delay circuitry, and forming a second feedback loop with the second delay circuitry, where the delay controller determines a difference between the first delayed clock signal and the second delayed clock signal and modifies the first control signal and the second control signal according to the determined difference.

Abstract: Various aspects of amplifying amplitude of a pulse are disclosed herein. In sonic embodiments, a device includes driver circuitry that receives an input pulse swinging or transitioning between a first reference voltage and a second reference voltage higher than the first reference voltage, In some embodiments, the driver circuitry generates a driving pulse swinging between a third reference voltage and the second reference voltage according to the input pulse, where the third reference voltage is between the first reference voltage and the second reference voltage. In some embodiments, the device further includes a transistor coupled to the driver circuitry. In some embodiments, the transistor outputs an output pulse swinging between the first reference voltage and an output voltage according to the driving pulse from the driver circuitry, where the output voltage is higher than the second reference voltage.

Abstract: Disclosed herein are embodiments of an apparatus and a method for generating a quadrature clock signal. In one aspect, the apparatus includes a first delay circuitry to delay a clock signal according to a first control signal to generate a first delayed clock signal. In one aspect, the apparatus includes a second delay circuitry to delay the clock signal according to a second control signal to generate a second delayed clock signal. In one aspect, the apparatus includes a delay controller forming a first feedback loop with the first delay circuitry, and forming a second feedback loop with the second delay circuitry, where the delay controller determines a difference between the first delayed clock signal and the second delayed clock signal and modifies the first control signal and the second control signal according to the determined difference.

Abstract: Systems and methods disclosed herein provide a coupled T-coil circuit for differential mode bandwidth extension and common mode rejection. The coupled T-coil circuit includes a first layer including at least a first portion of a first T-coil circuit and a first portion of a second T-coil circuit, and a second layer disposed on top of the first layer and interconnected to the first layer, the second layer including at least a second portion of the first T-coil circuit and a second portion of the second T-coil circuit. The first T-coil circuit includes one or more first coils with a first wind direction. The second T-coil circuit comprises one or more second coils with a second wind direction. The first wind direction can be opposite the second wind direction.

Abstract: Apparatus, system and method for driving asynchronous digital-to-analog circuits are provided. An apparatus including circuitry configured to receive an analog signal, determine a comparison signal based on the analog signal, convert the comparison signal to a digital signal, generate a comparison reset signal after a preset delay, determine a final comparison signal based on the digital signal, convert the final comparison signal to a final digital signal, and output the final comparison signal. The circuitry successively approximates the digital signal using a binary search.

Abstract: A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.

Abstract: A phase alignment architecture enhances the performance of communication systems. The architecture aligns a divided clock (e.g., in differential Inphase (I) and Quadrature (Q)) to a main clock, even at extremely high speeds, where skew variations of the divided clock are comparable to the main clock period. The improvement in phase alignment facilitates ultra high-speed communications.

Abstract: A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.

Abstract: Techniques are described herein that adaptively suppress harmonic distortion in an amplifier utilizing negative gain. The amplifier includes a first amplifier stage and a second amplifier stage, which are coupled in parallel. The first amplifier stage has a positive gain. The second amplifier stage has a negative gain to suppress total harmonic distortion of a system that includes the amplifier. The amplifier further includes shunt-peaking circuitry coupled to the first amplifier stage and the second amplifier stage to increase a maximum operating frequency at which the amplifier is capable of operating.

Abstract: A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.

Abstract: Methods and apparatuses are described for versatile phase adjustment schemes comprising multi-layered clock skew correction with variable range and resolution to improve performance for a variety of ADC architectures, including TI-ADCs. Multi-stage phase alignment corrects misalignment in multiple stages at start-up and continuously or periodically during operation to reduce static sources of misalignment caused by design and fabrication and dynamic sources of misalignment caused by operational variations (e.g., voltage, temperature). Multi-path phase alignment corrects misalignment in the data path (e.g., analog path) and the clock path (e.g., digital path, analog path, CMOS path, CML path, or any combination thereof) for distributed alignment. Multi-lane phase alignment corrects misalignment in multiple time-interleaved signal lanes. Multi-resolution phase alignment corrects misalignment at three or more levels of resolution (e.g., coarse, fine and ultra-fine).

Abstract: Methods and apparatuses are described for versatile phase adjustment schemes comprising multi-layered clock skew correction with variable range and resolution to improve performance for a variety of ADC architectures, including TI-ADCs. Multi-stage phase alignment corrects misalignment in multiple stages at start-up and continuously or periodically during operation to reduce static sources of misalignment caused by design and fabrication and dynamic sources of misalignment caused by operational variations (e.g., voltage, temperature). Multi-path phase alignment corrects misalignment in the data path (e.g., analog path) and the clock path (e.g., digital path, analog path, CMOS path, CML path, or any combination thereof) for distributed alignment. Multi-lane phase alignment corrects misalignment in multiple time-interleaved signal lanes. Multi-resolution phase alignment corrects misalignment at three or more levels of resolution (e.g., coarse, fine and ultra-fine).

Abstract: Techniques are described herein that adaptively suppress harmonic distortion in an amplifier utilizing negative gain. The amplifier includes a first amplifier stage and a second amplifier stage, which are coupled in parallel. The first amplifier stage has a positive gain. The second amplifier stage has a negative gain to suppress total harmonic distortion of a system that includes the amplifier. The amplifier further includes shunt-peaking circuitry coupled to the first amplifier stage and the second amplifier stage to increase a maximum operating frequency at which the amplifier is capable of operating.

Abstract: There is presented a high bandwidth circuit for high-speed transceivers. The circuit may comprise an amplifier combining capacitor splitting, inductance tree structures, and various bandwidth extension techniques such as shunt peaking, series peaking, and T-coil peaking to support data rates of 45 Gbs/s and above while reducing data jitter. The inductance elements of the inductance tree structures may also comprise high impedance transmission lines, simplifying implementation. Additionally, the readily identifiable metal structures of inductors and t-coils, the equal partitioning of the load capacitors, and the symmetrical inductance tree structures may simplify transceiver implementation for, but not limited to, a clock data recovery circuit.

Abstract: A first clock generator receives an input clock, generates a first clock signal for use in a first level of a multilevel track and hold circuit of a time-interleaved analog to digital convertor, and generates a time-leading version of the first clock signal. A plurality of second clock generators receive the input clock and generate a corresponding plurality of second clock signals for use in a second level of the multi-level track and hold circuit. The plurality of second level clock generators include an adjustable delay that delays a corresponding one of the plurality of second clock signals by a delay amount that is determined based on a delay control signal. A feedback controller generates the delay control signal based on the time-leading version of the first clock signal and further based on the corresponding one of the plurality of second clock signals.

Abstract: A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.

Abstract: A transmitting system includes a clock system and a data system. The clock system is configured to receive a clock having a first value and produce a control signal having a second, different value and an output clock having the first value. The data system is configured to receive data and the control signal and to align the data with the output clock, based on the control signal, to produce output data. The clock system includes a driver configured to produce the output clock, a divider configured to divide the received clock, and a phase interpolator configured to rotate the divided clock to produce the control signal. Also, the data is parallel data, and the data system includes a multiplexer configured to receive the parallel data and to use the control signal to serialize the parallel data as the aligned data and a driver configured to produce the output data.

Abstract: There is presented a high bandwidth circuit for high-speed transceivers. The circuit may comprise an amplifier combining capacitor splitting, inductance tree structures, and various bandwidth extension techniques such as shunt peaking, series peaking, and T-coil peaking to support data rates of 45 Gbs/s and above while reducing data jitter. The inductance elements of the inductance tree structures may also comprise high impedance transmission lines, simplifying implementation. Additionally, the readily identifiable metal structures of inductors and t-coils, the equal partitioning of the load capacitors, and the symmetrical inductance tree structures may simplify transceiver implementation for, but not limited to, a clock data recovery circuit.

Abstract: There is presented a high bandwidth circuit for high-speed transceivers. The circuit may comprise an amplifier combining capacitor splitting, inductance tree structures, and various bandwidth extension techniques such as shunt peaking, series peaking, and T-coil peaking to support data rates of 45 Gbs/s and above while reducing data jitter. The inductance elements of the inductance tree structures may also comprise high impedance transmission lines, simplifying implementation. Additionally, the readily identifiable metal structures of inductors and t-coils, the equal partitioning of the load capacitors, and the symmetrical inductance tree structures may simplify transceiver implementation for, but not limited to, a clock data recovery circuit.