Patents by Inventor Deming GU
Deming GU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11625587Abstract: An artificial intelligence integrated circuit is provided. The artificial intelligence integrated circuit includes a flash memory, a dynamic random access memory (DRAM), and a memory controller. The flash memory is configured to store a logical-to-physical mapping (L2P) table that is divided into a plurality of group-mapping (G2P) tables. The memory controller includes a first processing core and a second processing core. The first processing core receives a host access command from a host. When a specific G2P table corresponding to a specific logical address in the host access command is not stored in the DRAM, the first processing core determines whether the second processing core has loaded the specific G2P table from the flash memory to the DRAM according to the values in a first column in a first bit map and in a second column of a second bit map.Type: GrantFiled: January 17, 2020Date of Patent: April 11, 2023Assignee: GLENFLY TECHNOLOGY CO., LTD.Inventor: Deming Gu
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Patent number: 11513852Abstract: A data transferring apparatus and a method for transferring data with overlap are provided. The data transferring apparatus includes a command splitter circuit and a plurality of tile processing circuits. The command splitter circuit splits a block level transfer command into a plurality of tile transfer tasks. The command splitter circuit may issue the tile transfer tasks to the tile processing circuits in a plurality of batches. The tile processing circuits may execute the tile transfer tasks in a current batch, so as to read data of a plurality of corresponding tiles among a plurality of source tiles of a source block to the tile processing circuits. After all the tile transfer tasks in the current batch have been executed by the tile processing circuits, the command splitter circuit issues the tile transfer tasks in a next batch of the batches to the tile processing circuits.Type: GrantFiled: May 15, 2020Date of Patent: November 29, 2022Assignee: GlenFly Technology Co., Ltd.Inventors: Heng Que, Yuanfeng Wang, Deming Gu, Fengxia Wu
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Patent number: 11425403Abstract: The invention introduces a method for compressing texture tiles, which contains at least the following steps: lossless-compressing raw data of a texture tile; determining whether a length of the lossless-compression result of the raw data is greater than a target result; and when the length of the lossless-compression result of the raw data is greater than the target length, performing data-reduction control in layers for generating reduced data by reducing the raw data, and generating a lossless-compression result of the reduced data, thereby enabling the length of the lossless-compression result of the reduced data to be equal to the target length or shorter.Type: GrantFiled: January 28, 2021Date of Patent: August 23, 2022Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.Inventors: Yemao Shen, Deming Gu, Heng Que, Wei Zhang
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Patent number: 11409523Abstract: A graphics processing unit includes a sparse matrix detection unit, a register file, an assertion register, and a matrix calculation unit. The sparse matrix detection unit reads a plurality of matrices from a storage device and determines whether the matrices are zero matrices or non-zero matrices to output a determination result. The register file stores the plurality of matrices from the sparse matrix detection unit. The assertion register marks up the matrices according to the determination result, and outputs a mark result. The matrix calculation unit receives a matrix calculation instruction, reads the non-zero matrices in the plurality of matrices from the register file according to the mark result, and calculates the non-zero matrices.Type: GrantFiled: January 4, 2021Date of Patent: August 9, 2022Assignee: GLENFLY TECHNOLOGY CO., LTD.Inventors: Wei Zhang, Deming Gu
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Patent number: 11307609Abstract: A method provides data synchronization between a sensor hub and an application processor, which contains at least the following steps: generating and adding a plurality of absolute time stamps in a sensor-data stream; and generating and adding a plurality of pieces of sensor data and a plurality of relative time stamps in the sensor-data stream between the moments of generating each two adjacent absolute time stamps, wherein each relative time stamp is associated with one piece of sensor data.Type: GrantFiled: April 15, 2019Date of Patent: April 19, 2022Assignee: GlenFly Technology Co., Ltd.Inventors: Jiangze Chen, Dongxing Wu, Deming Gu, Guixiang He, Kangning Zhu
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Publication number: 20220100814Abstract: A graphics processor includes a texel unit and an execution unit. The texel unit includes a loading module. The execution unit includes an im2col module to execute an im2col algorithm to expand an original matrix to obtain an expansion matrix according to the size of a kernel. The execution unit multiplies the expansion matrix and the kernel to obtain a feature map matrix. The loading module calculates feature coordinates of each element of the feature map matrix according to the coordinates of the expansion matrix, and obtains the original coordinates of each element of the original matrix according to the feature coordinates, the size of the kernel, a stride, and padding. The loading module reads at least one of the memory blocks covered by the original coordinates of each element of the original matrix, and outputs data corresponding to the original coordinates in the memory blocks.Type: ApplicationFiled: April 13, 2021Publication date: March 31, 2022Inventors: Wei ZHANG, Deming GU
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Publication number: 20220004385Abstract: A graphics processing unit includes a sparse matrix detection unit, a register file, an assertion register, and a matrix calculation unit. The sparse matrix detection unit reads a plurality of matrices from a storage device and determines whether the matrices are zero matrices or non-zero matrices to output a determination result. The register file stores the plurality of matrices from the sparse matrix detection unit. The assertion register marks up the matrices according to the determination result, and outputs a mark result. The matrix calculation unit receives a matrix calculation instruction, reads the non-zero matrices in the plurality of matrices from the register file according to the mark result, and calculates the non-zero matrices.Type: ApplicationFiled: January 4, 2021Publication date: January 6, 2022Inventors: Wei ZHANG, Deming GU
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Publication number: 20210397934Abstract: A neural network computing device and a cache management method thereof are provided. The neural network computing device includes a computing circuit, a cache circuit and a main memory. The computing circuit performs a neural network calculation including a first layer calculation and a second layer calculation. After the computing circuit completes the first layer calculation and generates a first calculation result required for the second layer calculation, the cache circuit retains the first calculation result in the cache circuit until the second layer calculation is completed. After the second layer calculation is completed, the cache circuit invalidates the first calculation result retained in the cache circuit to prevent the first calculation result from being written into the main memory.Type: ApplicationFiled: August 11, 2020Publication date: December 23, 2021Applicant: GlenFly Technology Co., Ltd.Inventors: Deming GU, Wei ZHANG, Yuanfeng WANG, Guixiang HE
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Publication number: 20210271515Abstract: A data transferring apparatus and a method for transferring data with overlap are provided. The data transferring apparatus includes a command splitter circuit and a plurality of tile processing circuits. The command splitter circuit splits a block level transfer command into a plurality of tile transfer tasks. The command splitter circuit may issue the tile transfer tasks to the tile processing circuits in a plurality of batches. The tile processing circuits may execute the tile transfer tasks in a current batch, so as to read data of a plurality of corresponding tiles among a plurality of source tiles of a source block to the tile processing circuits. After all the tile transfer tasks in the current batch have been executed by the tile processing circuits, the command splitter circuit issues the tile transfer tasks in a next batch of the batches to the tile processing circuits.Type: ApplicationFiled: May 15, 2020Publication date: September 2, 2021Applicant: GlenFly Technology Co., Ltd.Inventors: Heng QUE, Yuanfeng WANG, Deming GU, Fengxia WU
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Publication number: 20210209451Abstract: An artificial intelligence integrated circuit is provided. The artificial intelligence integrated circuit includes a flash memory, a dynamic random access memory (DRAM), and a memory controller. The flash memory is configured to store a logical-to-physical mapping (L2P) table that is divided into a plurality of group-mapping (G2P) tables. The memory controller includes a first processing core and a second processing core. The first processing core receives a host access command from a host. When a specific G2P table corresponding to a specific logical address in the host access command is not stored in the DRAM, the first processing core determines whether the second processing core has loaded the specific G2P table from the flash memory to the DRAM according to the values in a first column in a first bit map and in a second column of a second bit map.Type: ApplicationFiled: January 17, 2020Publication date: July 8, 2021Inventor: DEMING GU
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Patent number: 11037268Abstract: A method for improving image quality by using multi-resolution is provided. The method includes: receiving an image data; dividing the image data into areas corresponding to different resolutions according to first parameter information, wherein the resolutions correspond to different frequencies; rendering the areas with the different frequencies in a single pass and outputting a rendered image data; and resolving the rendered image data into a final output image data with a first resolution according to second parameter information.Type: GrantFiled: June 19, 2017Date of Patent: June 15, 2021Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.Inventor: Deming Gu
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Publication number: 20210152838Abstract: The invention introduces a method for compressing texture tiles, which contains at least the following steps: lossless-compressing raw data of a texture tile; determining whether a length of the lossless-compression result of the raw data is greater than a target result; and when the length of the lossless-compression result of the raw data is greater than the target length, performing data-reduction control in layers for generating reduced data by reducing the raw data, and generating a lossless-compression result of the reduced data, thereby enabling the length of the lossless-compression result of the reduced data to be equal to the target length or shorter.Type: ApplicationFiled: January 28, 2021Publication date: May 20, 2021Inventors: Yemao SHEN, Deming GU, Heng QUE, Wei ZHANG
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Patent number: 10915982Abstract: A graphics processing unit (GPU) is provided. The GPU includes a command stream parser (CSP). The CSP receives a command list from a display driver and parses commands in the command list to determine a rendering mode of the GPU and perform a graphics rendering pipeline for graphics processing according to the rendering mode. When the CSP determines that at least a specific CSP command is not included in the command list, the CSP determines that the rendering mode is a first rendering mode. When the CSP determines that the specific CSP command is included in the command list, the CSP determines that the rendering mode is a second rendering mode. In the second rendering mode, the CSP divides a rendering target into tiles, obtains first drawing commands from the command list according to the specific CSP command, and executes the first drawing commands for each tile.Type: GrantFiled: January 16, 2019Date of Patent: February 9, 2021Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.Inventors: Ying Wang, Fengxia Wu, Deming Gu, Yi Zhou, Jiakuan Hu
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Patent number: 10679318Abstract: A graphics processing method is provided, adapted to a graphic processing unit, the steps including: receiving, via a CSP, a first command associated with all render targets from a display driver; determining, via the display driver, sizes and areas of a plurality of tiles in each frame; repeatedly controlling, via a scissor pool unit, a graphics processing unit to perform drawing processing for each tile according to the first command; comparing, via a signature comparing unit of a cache memory, a signature of a current tile of a current frame and a signature of a tile corresponding to the same position of a previous frame and generating a comparison result; and determining whether to flush the dirty data of the current tile stored in the cache memory from the cache memory to a memory access unit according to the comparison result.Type: GrantFiled: April 11, 2019Date of Patent: June 9, 2020Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.Inventors: Fengxia Wu, Deming Gu, Heng Que, Yi Zhou, Ying Wang
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Patent number: 10628911Abstract: A graphics processing unit (GPU) is provided. The GPU includes a command stream parser (CSP) including a profiling unit used to provide performance statistics data for the GPU to determine a rendering mode of the GPU, wherein the rendering mode includes a first rendering mode and a second rendering mode for performing a graphics rendering pipeline for graphics processing. The profiling unit calculates drawing time of frames and the number of objects in the frames when the GPU operates in the first rendering mode, and determines whether the operation of the GPU is switched to the second rendering mode according to the calculated drawing time and the number of objects; when determining that the calculated drawing time and the number of objects are less than their respective thresholds, the CSP causes the operation of the GPU to switch from the first rendering mode to the second rendering mode.Type: GrantFiled: January 16, 2019Date of Patent: April 21, 2020Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.Inventors: Ying Wang, Fengxia Wu, Deming Gu, Yi Zhou, Jiakuan Hu
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Publication number: 20200118239Abstract: A graphics processing method is provided, adapted to a graphic processing unit, the steps including: receiving, via a CSP, a first command associated with all render targets from a display driver; determining, via the display driver, sizes and areas of a plurality of tiles in each frame; repeatedly controlling, via a scissor pool unit, a graphics processing unit to perform drawing processing for each tile according to the first command; comparing, via a signature comparing unit of a cache memory, a signature of a current tile of a current frame and a signature of a tile corresponding to the same position of a previous frame and generating a comparison result; and determining whether to flush the dirty data of the current tile stored in the cache memory from the cache memory to a memory access unit according to the comparison result.Type: ApplicationFiled: April 11, 2019Publication date: April 16, 2020Inventors: Fengxia WU, Deming GU, Heng QUE, Yi ZHOU, Ying WANG
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Patent number: 10606335Abstract: A dynamic voltage frequency scaling (DVFS) system is provided. The DVFS system includes: a computation unit, a power management unit (PMU), a hardware activity monitor (HAM), and a hardware voltage monitor (HVM). The HAM monitors a working status and temperature information of the computation unit, and determines whether to update an operating voltage and frequency of the computation unit according to the working status, the temperature information, and a previous determination result. When the HAM determines to update the operating voltage and frequency, the HAM generates a first control signal to the PMU to calibrate the operating voltage and frequency. The HVM detects timing information of the computation unit and determine whether to fine-tune the operating voltage according to the detected timing information. When the HVM determines to fine-tune the operating voltage, the hardware monitor generates a second control signal to the PMU to fine-tune the operating voltage.Type: GrantFiled: December 12, 2014Date of Patent: March 31, 2020Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.Inventors: Deming Gu, Zhou Hong
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Publication number: 20200082493Abstract: A graphics processing unit (GPU) is provided. The GPU includes a command stream parser (CSP) including a profiling unit used to provide performance statistics data for the GPU to determine a rendering mode of the GPU, wherein the rendering mode includes a first rendering mode and a second rendering mode for performing a graphics rendering pipeline for graphics processing. The profiling unit calculates drawing time of frames and the number of objects in the frames when the GPU operates in the first rendering mode, and determines whether the operation of the GPU is switched to the second rendering mode according to the calculated drawing time and the number of objects; when determining that the calculated drawing time and the number of objects are less than their respective thresholds, the CSP causes the operation of the GPU to switch from the first rendering mode to the second rendering mode.Type: ApplicationFiled: January 16, 2019Publication date: March 12, 2020Inventors: Ying WANG, Fengxia WU, Deming GU, Yi ZHOU, Jiakuan HU
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Publication number: 20200082492Abstract: A graphics processing unit (GPU) is provided. The GPU includes a command stream parser (CSP). The CSP receives a command list from a display driver and parses commands in the command list to determine a rendering mode of the GPU and perform a graphics rendering pipeline for graphics processing according to the rendering mode. When the CSP determines that at least a specific CSP command is not included in the command list, the CSP determines that the rendering mode is a first rendering mode. When the CSP determines that the specific CSP command is included in the command list, the CSP determines that the rendering mode is a second rendering mode. In the second rendering mode, the CSP divides a rendering target into tiles, obtains first drawing commands from the command list according to the specific CSP command, and executes the first drawing commands for each tile.Type: ApplicationFiled: January 16, 2019Publication date: March 12, 2020Inventors: Ying WANG, Fengxia WU, Deming GU, Yi ZHOU, Jiakuan HU
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Patent number: 10482850Abstract: A method for improving image quality is provided. The method includes: receiving an image data and sensing information; dividing the image data into areas corresponding to different resolutions according to first parameter information, wherein the different resolutions correspond to different frequencies; rendering the areas in a single pass according to the sensing information and the different frequencies and outputting a rendered image data; and resolving the rendered image data into a final output image data with a first resolution according to second parameter information.Type: GrantFiled: June 19, 2017Date of Patent: November 19, 2019Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.Inventors: Deming Gu, Fengxia Wu, Huaisheng Zhang, Wei Zhang