Abstract: A method for selectively etching a tungsten layer on a substrate includes arranging a substrate including a tungsten layer on a substrate support. The substrate processing chamber includes an upper chamber region, an inductive coil arranged outside of the upper chamber region, a lower chamber region including the substrate support and a gas dispersion device arranged between the upper and lower chamber regions. The gas dispersion device includes a plurality of holes in fluid communication with the upper and lower chamber regions. The method further includes controlling pressure in the substrate processing chamber in a range from 0.4 Torr to 10 Torr; supplying an etch gas mixture including fluorine-based gas to the upper chamber region; striking inductively coupled plasma in the upper chamber region by supplying power to the inductive coil; and selectively etching the tungsten layer relative to at least one other film material of the substrate.

Abstract: A method for providing a FinFET device with an air gap spacer includes providing a substrate a plurality of fins and a dummy gate arranged transverse to the plurality of fins; depositing a sacrificial spacer around the dummy gate; depositing a first interlayer dielectric (ILD) layer around the sacrificial spacer; selectively etching the dummy polysilicon gate relative to the first ILD layer and the sacrificial spacer; depositing a replacement metal gate (RMG); etching a portion of the RMG to create a recess surrounded by the sacrificial spacer; and depositing a gate capping layer in the recess. The gate capping layer is at least partially surrounded by the sacrificial spacer and is made of silicon oxycarbide (SiOC).

Abstract: A method for providing a FinFET device with an air gap spacer includes providing a substrate a plurality of fins and a dummy gate arranged transverse to the plurality of fins; depositing a sacrificial spacer around the dummy gate; depositing a first interlayer dielectric (ILD) layer around the sacrificial spacer; selectively etching the dummy polysilicon gate relative to the first ILD layer and the sacrificial spacer; depositing a replacement metal gate (RMG); etching a portion of the RMG to create a recess surrounded by the sacrificial spacer; and depositing a gate capping layer in the recess. The gate capping layer is at least partially surrounded by the sacrificial spacer and is made of silicon oxycarbide (SiOC).

Abstract: Provided are methods and apparatuses for removing a polysilicon layer on a wafer, where the wafer can include a nitride layer, a low-k dielectric layer, an oxide layer, and other films. A plasma of a hydrogen-based species and a fluorine-based species is generated in a remote plasma source, and the wafer is exposed to the plasma at a relatively low temperature to limit the formation of solid byproduct. In some implementations, the wafer is maintained at a temperature below about 60° C. The polysilicon layer is removed at a very high etch rate, and the selectivity of polysilicon over the nitride layer and the oxide layer is very high. In some implementations, the wafer is supported on a wafer support having a plurality of thermal zones configured to define a plurality of different temperatures across the wafer.

Abstract: An embodiment of the invention is an organic thin film transistor chemical sensor. The sensor includes a substrate. A gate electrode is isolated from drain and source electrodes by gate dielectric. An organic ultra-thin semiconductor thin film is arranged with respect to the gate, source and drain electrodes to act as a conduction channel in response to appropriate gate, source and drain potentials. The organic ultra-thin film is permeable to a chemical analyte of interest and consists of one or a few atomic or molecular monolayers of material. An example sensor array system includes a plurality of sensors of the invention. In a preferred embodiment, a sensor chip having a plurality of sensors is mounted in a socket, for example by wire bonding. The socket provides thermal and electrical interference isolation for the sensor chip from associated sensing circuitry that is mounted on a common substrate, such as a PCB (printed circuit board).

Abstract: Substrate devices having tuned work functions and methods of forming thereof are provided. In some embodiments, forming devices on substrates may include depositing a dielectric layer atop a substrate having a conductivity well; depositing a work function layer comprising titanium aluminum or titanium aluminum nitride having a first nitrogen composition atop the dielectric layer; etching the work function layer to selectively remove at least a portion of the work function layer from atop the dielectric layer; depositing a layer comprising titanium aluminum or titanium aluminum nitride having a second nitrogen composition atop the work function layer and the substrate, wherein at least one of the work function layer or the layer comprises nitrogen; etching the layer and the dielectric layer to selectively remove a portion of the layer and the dielectric layer from atop the substrate; and annealing the substrate at a temperature less than about 1500 degrees Celsius.

Abstract: Substrate devices having tuned work functions and methods of forming thereof are provided. In some embodiments, forming devices on substrates may include depositing a dielectric layer atop a substrate having a conductivity well; depositing a work function layer comprising titanium aluminum or titanium aluminum nitride having a first nitrogen composition atop the dielectric layer; etching the work function layer to selectively remove at least a portion of the work function layer from atop the dielectric layer; depositing a layer comprising titanium aluminum or titanium aluminum nitride having a second nitrogen composition atop the work function layer and the substrate, wherein at least one of the work function layer or the layer comprises nitrogen; etching the layer and the dielectric layer to selectively remove a portion of the layer and the dielectric layer from atop the substrate; and annealing the substrate at a temperature less than about 1500 degrees Celsius.

Abstract: An embodiment of the invention is an organic thin film transistor chemical sensor. The sensor includes a substrate. A gate electrode is isolated from drain and source electrodes by gate dielectric. An organic ultra-thin semiconductor thin film is arranged with respect to the gate, source and drain electrodes to act as a conduction channel in response to appropriate gate, source and drain potentials. The organic ultra-thin film is permeable to a chemical analyte of interest and consists of one or a few atomic or molecular monolayers of material. An example sensor array system includes a plurality of sensors of the invention. In a preferred embodiment, a sensor chip having a plurality of sensors is mounted in a socket, for example by wire bonding. The socket provides thermal and electrical interference isolation for the sensor chip from associated sensing circuitry that is mounted on a common substrate, such as a PCB (printed circuit board).