Abstract: A PCI interface is provided to support a 16- or 32-bit PCI host employing little-endian or big-endian byte ordering. The PCI interface may be arranged on a multiport switch to enable a PCI host to access internal registers and an external memory via a PCI bus. When a 16-bit PCI host is provided with access to a 32-bit internal register, two consecutive 16-bit data transfers are performed. The first 16 bits of data are temporarily stored in a holding register until the following 16 bits are transferred. The PCI host accesses the external memory via posting write buffers and prefetch read buffers arranged between an external memory interface and the PCI interface. When the multiport switch is configured to support a big-endian PCI host, bytes of a word transferred between the external memory and a write or read buffer are swapped to rearrange byte ordering of the word.

Abstract: A network switch configured for switching data packets across multiple switch ports uses programmable hash functions to generate a hash key for each network address to access an address table storing switching logic. The address table is configured to include a programmable number of bin entries, where each bin entry is configured to reference a plurality of address table entries storing the switching logic information for respective network addresses. The address of an incoming data packet is used to generate a hash key that references a selected one of the bin entries. The switching logic for the corresponding address is then obtained by accessing the appropriate table entry referenced by the selected bin entry. If the number of table entries for a given bin exceeds a prescribed threshold, an external host reprograms the network switch to use another hash key to maintain an efficient access throughput of the address table.

Abstract: A network switch configured for switching data packets across multiple ports uses an address table to generated frame forwarding information. The switch receives frame information including a source address and destination address along with a virtual local area network (VLAN) ID, if applicable. Hash keys for the source address and destination address are generated. A decision-making engine receives the source address, destination address, receive port number, hash keys and VLAN ID and searches a network address table to generate frame forwarding information.

Abstract: A method and apparatus for programmably driving a light-emitting diode(LED) display stores a display configuration in a register. The register contains the information identifying for which conditions in the system will status information be provided to LED drivers. When used in a system such as an Ethernet network multiport switch, for example, the status information for only those conditions and those ports identified by the display configuration stored in the configuration register will be displayed, even though status is collected for more conditions in the system.

Abstract: A multiport data network switch includes a programmable Management Information Base (MIB) configuration register that serves as a reference for the Media Access Controller (MAC) at each port. The register is programmable for maximum packet length in two configurations. In a first configuration, the maximum packet length setting is constant for all ports. In the second configuration, the maximum packet length is set at a plurality of levels in accordance with certain dynamic conditions. On an untagged port, or on a tagged port capable of communicating with a Virtual Local Area Network (VLAN) that receives/transmits an untagged frame, the maximum packet length criterion is a first value. On a tagged port that receives/transmits a VLAN tagged frame, the maximum packet length criterion first level is expanded by the number of bytes required for the VLAN tag.

Abstract: A resetting, enabling and freezing system is provided for controlling a communication device in a diagnostic process. A hardware reset of the device may be performed by a host via a reset pin of a PCI interface. A software reset of the device may be provided by setting a reset bit in a command register. To stop operations of the device substantially instantaneously, a freeze mode of diagnostics is provided. The freeze mode may be initiated using hardware or software freezing. To provide the hardware freezing, diagnostic logic is supplied with a freeze signal via a freeze pin of the PCI interface. The software freezing is performed by setting a freeze bit in the command register. To enable a diagnostician to reproduce an event causing an error, an enable/disable mode of diagnostics is carried out. In this mode, elements of the device are disabled one after another in a serial fashion, with a disable signal being passed serially from one element to another.

Abstract: A network switch having a shared memory architecture for storing data frames has a set of programmable thresholds that specify when flow control should be initiated on a selected network port. The network switch includes a queue for storing free frame pointers, each specifying available memory locations in an external memory for storing data frames received from a network station. The network switch takes a frame pointer from a free buffer queue for each received data frame, and stores the received data frame in the location in external memory specified by the frame pointer while a decision making engine within the switch determines the appropriate destination ports.

Abstract: Write posting buffers and read prefetch buffers are arranged in an integrated multiport switch between a PCI interface and an external memory interface. When a PCI host initiates a PCI transaction to write data from an external memory, the data provided by the PCI host is written into the write posting buffers. Then, the contents of the write posting buffers is transferred to the external memory. The read prefetch buffers are used to temporarily store data prefetched in anticipation of a PCI transaction initiated by the PCI host to read that data from the external memory. When the PCI host initiates the read transaction, the address of the requested data is compared with the address of the prefetched data to transfer the prefetched data to the host if a match is detected. In an auto-prefetch mode, data is automatically prefetched from the external memory when an extension bus port output queue contains a frame pointer for a frame queued for transmission over the PCI interface to the PCI host.

Abstract: A network having a shared memory architecture for storing data frames has a set of programmable thresholds that specify when flow control should be initiated on full-duplex network ports. The network switch includes a queue for storing free frame pointers that specify available memory locations in an external memory for storing data frames received from a network station. The network switch takes a frame pointer from a free buffer queue for each received data frame, and stores the received data frame in the location in external memory specified by the frame pointer while a decision making engine within the switch determines the appropriate destination ports. Flow control is initiated based on the number of available frame pointers by transmitting a PAUSE frame having a selected PAUSE interval to a transmitting network station.

Abstract: Management data is selectively supplied to a management agent by a network switch using either a media access control (MAC) layer interface or PCI bus interface to provide maximum flexibility for the management agent. The management data includes management packets having at least a portion of a received data packet, and management information specifying receive status and network switch response characteristics to the corresponding received data packet. The network switch includes a plurality of network ports, including network traffic ports and one management queue for selectively supplying the management data to either the PCI interface or the management MAC interface. The selective output of the management frame via the alternate output paths enables the disclosed network switch to be implemented in existing switch fabric that uses a predetermined management protocol. The paths may also be segregated to optimize bandwidth for high priority data and low priority data, respectively.

Abstract: Management data is supplied to a management agent by a network switch by generating management packets having at least a portion of a received data packet, and management information specifying receive status and network switch response characteristics to the corresponding received data packet. The network switch includes a plurality of network ports, including network traffic ports and one management port for synthesizing the management frame. A network traffic port receiving a data packet generates receive status data specifying the reception status of the received data packet, including the presence of cyclic redundancy check (CRC) errors, frame alignment errors, and receive buffer overflow conditions. The received data packet and received status data are stored in a buffer memory, while switching logic generates port vectors specifying destination output ports and switching logic data specifying the switching logic response to the received data packet.

Abstract: An interface device enables an external device connected to a network switch to be disabled. The interface device receives and transmits data to an external device which makes data forwarding decisions. When a disable signal is received by the network switch, the disable signal is transmitted to the external device over an existing data path. The external device returns an acknowledgement signal over an existing path to the switch. A timer is included as a failsafe mechanism in case the external device does not return an acknowledge signal. The timer waits a predetermined period of time and continues the shut down of the network switch as if the acknowledge signal was received.

Abstract: A network switch configured for switching data packets across multiple ports uses an address table to generate frame forwarding information. A decision-making engine receives a source address, destination address and receive port number along with a virtual local area network (VLAN) ID, if applicable. The decision-making engine searches the address table twice to generate frame forwarding information. The first search is based on the source address and the receive port number of the frame and the second search is based on the destination address and a VLAN index for the received frame. The network switch uses the information generated from the searches to generate the frame forwarding information.

Abstract: An interface located on a network switch transmits header information to an external device that makes data forwarding decisions. The interface receives and transmits header information that includes the source and destination address of the data. The external device generates data forwarding information and transmits the information back to the switch via the interface device. The network switch uses the information obtained via the interface and forwards the data packets to the appropriate destination.

Abstract: A network switch configured for switching data packets across multiple switch ports includes in each network switch port a hash key generator configured to generate a hash key for each network address in a received data packet. Each data packet received by a network switch port includes a source address and a destination address according to IEEE 802.3 protocol. The hash key generator in the corresponding network switch port generates the hash key for the source and destination addresses as the data packet is received by the network switch port, minimizing processing latency in generating the hash key. The hash keys are forwarded to an address table configured to include a programmable number of bin entries, where each bin entry is configured to reference a plurality of address table entries storing the switching logic information for respective network addresses.

Abstract: A network switch data decision making engine is diagnosed while the switch is operating or after an error is detected. The switch receives data from connected stations and sends header information to the decision making engine. The header information is simultaneously transmitted to an external device. The decision making engine generates a data forwarding decision and outputs the decision to the external device. The operation of the decision making engine can then be checked by an external crevice, such as a logic analyzer.

Abstract: Every external physical layer device coupled to a multiport data communication switch is polled in succession to determine status and control information relating to the external physical layer device. The polling procedure performed automatically at regular time intervals is interleaved with management accesses to the external PHYs initiated by a host processor. The host management access may be performed to write or read management data to or from a particular register in a particular external physical layer device.

Abstract: An interrupt system having three tiers is provided. The first tier includes individual interrupt and enable registers, each of which provides multiple local interrupt signals in response to various events in a multiport switch. Local enable signals are supplied to the individual interrupt and enable registers to enable the local interrupt signals to be written into a global interrupt status register that provides the second tier of the interrupt system. The global interrupt status register produces several global interrupt signals, each of which represents one of the individual interrupt and enable registers. The third tier of the interrupt system includes a switch command register that generates an interrupt pending signal if any one of the global interrupt signals is produced. A global enable signal provided by the host processor enables the switch command register to produce an interrupt request signal to be supplied to a host processor.

Abstract: An apparatus and method of controlling the transmission of copies of a frame of data from a multiport device, such as a multiport network switch, determines which ones of the ports are designated to transmit a copy of a multicopy frame received at the switch. The switch then determines which of these designated ports are not available to transmit a copy of the frame. The copies are transmitted from those designated ports that are available to transmit a copy of the multicopy frame, while the copies are discarded for those designated ports that are not available to transmit a copy of that multicopy frame.