Abstract: A system and method transmits data and receives data packets within a bonding engine. The data packets are fragmented into a plurality of packet fragments for communication across a bonded group of subscriber lines. A Frame Check Sequence (FCS) in the data packet is inverted on one direction of the bonding group to prevent any data packets from propagating towards the network during a loopback condition.

Abstract: A system and method transmits data and receives data packets within a bonding engine. The data packets are fragmented into a plurality of packet fragments for communication across a bonded group of subscriber lines. A Frame Check Sequence (FCS) in the data packet is inverted on one direction of the bonding group to prevent any data packets from propagating towards the network during a loopback condition.

Abstract: A data transmission scheduler subsystem for a multi-channel bank communication system architecture contains a plurality of ‘per port’ schedulers. Each per port scheduler is resident in the system's primary channel bank, and is operative to controllably cause customer-destined data, that has been buffered from a communication network into switch fabric storage circuitry of the primary channel bank, to be controllably read out for downlink transmission to associated destination data ports of the channel banks at the destination data ports' data rates.

Abstract: A policing engine for use in a telecommunication equipment shelf is operative to control the rate at which customer-sourced ATM packets are passed to buffers associated with different classes of service to which customers may subscribe. The policing engine examines the rate at which ATM cells are supplied to it from the line card ports, whether the cells are AAL5 cells, and how full are the buffers into which the cells are to be written. If cells are supplied to the policing engine at a rate faster than prescribed peak or sustained cell rates, or if the cell buffer begins to fill up, the policing engine controllably discards incoming cells, thereby effectively ‘throttling’ the cell flow rate through it.

Abstract: A single switch fabric-based, multi-channel bank digital subscriber line access multiplexer includes a master channel bank containing a master switch module in which the switch fabric and a downstream-directed traffic scheduler reside, and one or more expansion channel banks that are linked with the master channel bank by way of upstream and downstream communication links. Distributed among the channel banks are respective policing mechanisms and cell rate control mechanisms that control upstream-directed communications from line card ports of each expansion channel bank to the switch fabric. Downstream data transmissions are locked to network timing, and are scheduled by a centralized scheduling mechanism resident in the master channel bank.

Abstract: An inter-channel bank addressing and identification protocol, for use with a multi channel bank, digital subscriber line access multiplexer (DSLAM), enables the control processor of a master channel bank to selectively communicate with control processors of subtended slave channel banks, and allows a subtended slave shelf to retain provisioning information, irrespective of a change in shelf location or removal of a subtended slave shelf between the master shelf and another subtended slave shelf. The inter-channel bank addressing and identification protocol uses a shelf address code that is controllably incremented or decremented during the transport of a packet between the master and a slave shelf. In addition, a shelf address code is assigned each slave shelf during initialization. These two codes enable the master to track which channel bank is in which shelf bay.

Abstract: A voice playout buffer for a dual PHY-based integrated access device platform has a plurality of voice signal buffer sections. A respective buffer section has a capacity in excess of the number of digitized voice signal bytes contained in a respective cell-based communication signal. The storage capacity of a buffer section accommodates a communications control processor writing new outgoing digitized voice signal bytes into the first portion of the voice signal buffer section for transport over a TDM communication link, prior to digitized voice signals newly received from the TDM communication link being written into the first portion of the voice signal buffer section.

Abstract: A back-up channel line card-installed ESF framing mechanism independently sources an FDL signaling channel for the transport of protection switch signaling information, taking advantage of the fact that DSL multiplexer equipment is capable of accepting and processing ESF framed digital data, including embedded FDL-based signaling information. Upon completion of transport of the FDL-based signaling information, the back-up channel is used for data transport in place of a faulty channel.

Abstract: A digital subscriber loop line card-installed mechanism conducts parametric measurements on the wireline to which the line card is connected, and adjusts taps of an echo cancellation operator in accordance with the response of the wireline to an electrical stimulus imparted to the wireline. The echo canceler tap coefficients are then processed to determine the location of a fault, such as a short circuit, open-circuit and the like, on the wireline. Fault information measurement data is then reported to a supervisory control location, which dispatches the appropriate technician to resolve the cause of the problem.

Abstract: A method and apparatus for removing glitches, interference or noise from a clock signal are provided by the present invention. In accordance with the invention, a glitch-ridden clock signal is monitored to determine when a transition in the glitch ridden clock signal occurs. When a transition occurs, a counter is initiated in accordance with a second high-speed clock signal. The value of this counter is compared to a compare value. The compare value is selected to approximately equal the expected period of the glitch-ridden clock signal. If the counter value equals the compare value, it is assumed that the transition was a valid transition and the transition is carried through and output as a glitch-free clock signal. However, if a transition occurs before the count value equals the counter compare value, it is assumed that the transition is invalid and no transition is carried to the glitch-free clock output.

Abstract: A voice playout buffer for a dual PHY-based integrated access device platform has a plurality of voice signal buffer sections. A respective buffer section has a capacity in excess of the number of digitized voice signal bytes contained in a respective cell-based communication signal. A respective buffer section sequentially stores digitized voice signals of a single TDM channel into successive storage locations of a first portion thereof at a first data rate, and reads out digitized voice signals at a second, higher data rate for transport over an ATM cell bus. The storage capacity of a buffer section accommodates a communications control processor writing new outgoing digitized voice signal bytes into the first portion of the voice signal buffer section for transport over a TDM communication link, prior to digitized voice signals newly received from the TDM communication link being written into the first portion of the voice signal buffer section.

Abstract: A back-up channel line card-installed ESF framing mechanism independently sources an FDL signaling channel for the transport of protection switch signaling information, taking advantage of the fact that DSL multiplexer equipment is capable of accepting and processing ESF framed digital data, including embedded FDL-based signaling information. Upon completion of transport of the FDL-based signaling information, the back-up channel is used for data transport in place of a faulty channel.

Abstract: A method and apparatus for removing glitches, interference or noise from a clock signal are provided by the present invention. In accordance with the invention, a glitch-ridden clock signal is monitored to determine when a transition in the glitch ridden clock signal occurs. When a transition occurs, a counter is initiated in accordance with a second high-speed clock signal. The value of this counter is compared to a compare value. The compare value is selected to approximately equal the expected period of the glitch-ridden clock signal. If the counter value equals the compare value, it is assumed that the transition was a valid transition and the transition is carried through and output as a glitch-free clock signal. However, if a transition occurs before the count value equals the counter compare value, it is assumed that the transition is invalid and no transition is carried to the glitch-free clock output.

Abstract: A method, system and apparatus for decreasing the time frame synchronization and resynchronization in a data communication uses an long frame sync word formed by combining a frame sync word with stuff bits, wherein the stuff bits are necessary for timing adjustments.

Abstract: A method and system for interfacing a transmission facility with a digital subscriber line to enable transmission of digital voice communication and associated digital signalling are provided. A digital signal from the digital subscriber line is demultiplexed into a digital communication signal and a digital input control signal having a first sequence providing standard framing pattern, a second sequence providing signalling identification, and a third sequence providing signalling information. A monitor monitors the sequence of the input control signal and produces a signalling identification detect signal when the second sequence is detected and signalling enablement output when the third sequence is detected. The communication signal from the digital subscriber line is selectively multiplexed with the signalling information from the input control signal. The signalling information is output to the transmission facility when the signalling-enablement output is produced by the monitor.

Abstract: A modem capable of simultaneously transmitting and receiving data signals over a single communication channel with a remote modem includes a transmitter for converting TX digital data into analog signals for transmission over the channel and a receiver for converting received analog signals into RX digital data. A mechanism identifies a remote echo returning to the modem corresponding to previously transmitted TX digital data. The identifiying mechanism is capable of identifiying a echo originating intermediate between the modem and the remote modem. Another mechanism substantially cancels the identified remote echo. The present invention also encompasses the method of identification and cancellation of remote echos. In addition, remote echo cancellation signals are not combined with received signals until local echo has been substantially cancelled.

Abstract: In a digital data receiver, it is desirable to use the equalized data for deriving time synchronization information. This invention minimizes timing contention between an equalizer operating at a T/2 rate and a timing recovery circuit which utilizes the output of the equalizer. An interpolator interpolates T1 and T2 data samples from the equalizer and provides data signals R and S equally spaced relative to the peak baud amplitude which can be easily processed by the timing recovery circuit.