Abstract: The Present disclosure is related to hot-mix asphalt (“HMA”) which open new price/performance areas to asphalt cement concrete (“ACC”) pavement. Equivalent-performing pavement may be made at lower cost, or higher-performing pavement may be made at equivalent-to-prior-art cost. The amendments, recycled asphalt pavement (“RAP”, and including recycled asphalt shingles [“RAS”]), and reinforcing fiber (aramid fiber) may be adjusted as described herein to achieve a desired price/performance target.

Abstract: Systems and methods are disclosed herein for puncturing Polar-encoded bits. In some embodiments, a method of operation of a radio node that utilizes a Polar encoder comprising performing Polar encoding of a plurality of bits to provide a plurality of Polar-encoded code bits and puncturing the plurality of Polar-encoded code bits using a hybrid puncturing scheme to provide a plurality of rate-matched Polar-encoded code bits, wherein the hybrid puncturing scheme uses different puncturing patterns for different code rate regions.

Abstract: According to some embodiments, a method of operation of a wireless transmitter in a wireless communication network comprises: encoding a set of information carrying data bits u of length K with a linear outer code to generate a set of outer parity bits p along with the data bits u; interleaving the set of outer parity bits p and the data bits u using a predetermined interleaving mapping function that depends on the number of data bits K and is operable to distribute some bits of the set of parity bits p in front of some data bits u; and encoding the interleaved bits using a Polar encoder to generate a set of encoded bits x. Various interleaving mapping functions are disclosed.

Abstract: According to some embodiments, a method for use in a wireless transmitter comprises: determining an amount of data to transmit; determining a cyclic redundancy check (CRC) polynomial length based on the amount of data to transmit; encoding the data using a CRC of the determined polynomial length; and transmitting the encoded data. According to some embodiments, a method for use in a wireless receiver comprises: receiving encoded data from a wireless transmitter; determining an amount of data received in the encoded data; determining a CRC polynomial length based on the amount of data; and decoding the received encoded data using a CRC of the determined polynomial length. In particular embodiments, the data to transmit comprises control channel data or user data, and the encoding uses Polar codes or low-density parity check (LDPC) codes.

Abstract: In one embodiment, a memory system is disclosed. The memory system has at least one memory chip having an address and data interface coupled to an internal address and data bus, and a memory controller and interface chip also having a an address and data interface coupled to the address and data interface of the at least one memory chip via an internal address and data bus. The at least one memory chip, the memory controller and interface chip and the internal address and data bus are disposed within a common chip package. The memory controller and interface chip has an external interface configured to be coupled to a standard memory bus via external contacts of the common chip package.

Abstract: In one embodiment, a memory system is disclosed. The memory system has at least one memory chip having an address and data interface coupled to an internal address and data bus, and a memory controller and interface chip also having a an address and data interface coupled to the address and data interface of the at least one memory chip via an internal address and data bus. The at least one memory chip, the memory controller and interface chip and the internal address and data bus are disposed within a common chip package. The memory controller and interface chip has an external interface configured to be coupled to a standard memory bus via external contacts of the common chip package.

Abstract: A method for selecting an active router in a communication device includes providing multiple routers in the device, coupling the routers to a single physical link, monitoring a status for each of the routers, and selecting one of the routers as an active router by positioning its corresponding relay.

Abstract: A method for communicating data packets is provided that includes receiving a data packet at a first processor. A packet handle and interface handle are attached to the data packet. The packet handle, interface handle, and data packet are communicated to a second processor. A plurality of data packets that are destined for the same output are multiplexed. At least one packet handle, one interface handle, and the multiplexed data packet are communicated to the first processor, and the multiplexed data packet is output.

Abstract: A multi-port RAM (MPRAM) having a SRAM and a DRAM on a single chip. Separate pins are provided on the chip to supply independent chip select signals for the SRAM and the DRAM. When the SRAM chip select signal is at a high level, a clock generator is prevented from producing an internal clock signal for the SRAM. As a result, no SRAM operation is performed in response to a SRAM command. Similarly, when the DRAM chip select signal is high, a clock generator produces no internal clock signal for the DRAM. As a result, DRAM operations are prevented from being performed in response to DRAM commands.

Abstract: A SRAM storage cell has a NMOS transistor and a PMOS transistor connected with each other between a source of potential and ground. The sources, gates and gate back plates of the transistors are commonly connected and coupled to a storage node. The drain of the NMOS transistor is supplied with the potential, whereas the drain of the PMOS transistor is grounded. A pass NMOS transistor is connected between the storage node and bit and word lines. This storage cell configuration provides considerably reduced area compared to conventional static storage cells.

Abstract: An output buffer is provided to output data read out from a memory array. The output buffer is composed of a main amplifier and an output driver. An input latch stage of the main amplifier is connected to an output of a preamplifier that reads out data from the memory array. A level shifter is coupled to the input latch stage to drive one of transistors in a transistor pair of the output driver. A driver stage is coupled to the input latch stage to drive another transistor in the output driver transistor pair. An output enable signal is supplied to the level shifter and to the driver stage to control the output driver. When the output enable signal is set to a first logic level, the output driver supplies valid data to an external device. When the output enable signal is at a second logic level, the output of the output driver is brought to a floating high-impedance state to disable data output.

Abstract: The power consumed by repetitive switching and precharging of a DRAM bus during repetitive write cycles is reduced by latching the data lines to the DRAM array during repeated data writes in a way which avoids the necessity of precharging the lines before every write. A fast write mode is invoked when repeated writes are to occur and is cleared at the end of the repeated writes.