Abstract: A memory device with a dynamic random access memory (DRAM) having an array of a plurality of rows and columns of memory elements; a cache memory formed integrally with the DRAM and includinmg at least one register with a plurality of memory elements and connected in pitch-matched relation to the DRAM array, the number of memory elements in a row of the DRAM being n times the number of memory elements in the at least one register, n being an integer greater than or equal to 2; and a connector for connecting the at least one register to the DRAM, the connector for the at least one register being a bus having a width corresponding to the number of memory elements therein.

Abstract: A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.

Abstract: A computer based video/graphics display system includes a computer system having a graphics generator. A video signal from a video source is fed through an input stage to an asynchronous converter. The converter synchronizes the video signal to the graphics generator. The output from the asynchronous converter and the output from the graphics generator are fed to a fading/mixing matrix. The combined signal output from the fading/mixing matrix is fed to a computer display monitor. The display monitor is synchronized to the graphics generator, and the video signal is input asynchronously. Circuitry is provided for displaying at least a portion of the video image together with the graphics image on the display. One or more video images can be manipulated, stored, and displayed in window areas on the display monitor. A picture can be built-up by combining several still images. The system allows the mixing and windowing of computer graphics and one or more video images together on the screen.

Abstract: A base board 10 carries four daughter cards 12a, 12b, 12c and 12d. Three of the daughter boards 12a, 12b, 12c are stacked on the front side of the base board 10, and the fourth daughter board 12d is carried on the rear side of the base board 10. Modifying means are provided on the daughter cards for modifying addresses sent from the base card to the daughter cards. This allows the daughter cards 12 to be identical, and still enables individual addressing of the daughter boards according to their position in the stack.

Abstract: A computer based video/graphics display system includes a computer system (22) having a graphics generator (24). A video signal from a video source (28) is fed through an input stage (26) to an asynchronous converter (30). The converter (30) synchronises the video signal to the graphics generator (24). The output from the asynchronous converter (30) and the output from the graphics generator (24) are fed to a fading/mixing matrix (34). The combined signal output from the fading/mixing matrix is fed to a computer display monitor (14). The system allows the mixing or windowing of computer graphics and a video image on a common display.

Abstract: A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.

Abstract: A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.

Abstract: A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.